Process for fabricating a aligned LDD transistor

Details Process for fabricating a aligned LDD transistor Process for fabricating a aligned LDD transistor

2001-03-30

2002-08-20

Weiss, Howard (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000

Reexamination Certificate

active

06436776

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-069897, filed Mar. 16, 1999; and No. 11-076355, Mar. 19, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a MOS-type transistor or a MIS-type transistor and to a MOS-type transistor or a MIS-type transistor. More specifically, it relates to the method of forming a diffusion layer in the salicide process and to a MOS-type transistor or a MIS-type transistor which will be obtained by this method.
As a result of an increasing demand in recent years for speeding-up as well as for the realization of high performance, the formation of low-resistance refractory metal silicide film, such as TiSi
2
and CoSi
2
, on the gate electrode and on the source-drain diffusion layer by self-alignment with the gate electrode is now being practiced. This is called the salicide structure. On the other hand there is a strong demand for miniaturization which makes it indispensable to form a diffusion area thinly on the semiconductor substrate.
Conventionally the salicide structure has been manufactured as follows. First form a polycrystal silicon layer on a silicon substrate
1
through a gate insulating film
2
, and form a gate electrode
3
by patterning it (FIG.
1
A). Then form a shallow impurity diffusion layer
4
by the ion-implantation of impurity by using the gate electrode
3
as a mask (FIG.
1
B).
Next, form a silicon nitride film on the entire surface of a substrate, and form a side-wall insulating film
5
on the side walls of a gate electrode
3
by implementing anisotropic etching, such as reactive ion etching (RIE). Then form a deep impurity diffusion layer
6
by the ion-implantation of impurity by using the side-wall insulating film
5
as a mask, and at the same time introduce impurity into the gate electrode
3
(
FIG. 1D
)
After this, heat the entire structure to activate the impurity in the gate electrodes
3
and also the impurity in the impurity diffusion layers
4
and
6
at the same time. This process forms a shallow diffusion layer
7
, adjacent to the gate electrode, having the so-called extension structure with a high-impurity concentration (FIG.
1
E).
As the condition for activating the impurity, however, it is necessary to activate the impurity in the polycrystal silicon, which is the gate electrode, as well as the impurity in the deep impurity diffusion layer
6
, all at the same time. Therefore, high temperature is required for this process, thus diffusing the shallow impurity diffusion layer
4
to a comparatively deep depth and making it difficult to maintain the shallow impurity diffusion layer at the shallow depth.
Next, form a silicide film
8
on the upper side of the gate electrode
3
and on the exposed surface of the impurity diffusion layer
7
(FIG.
1
F).
As described above, the conventional technology has formed the shallow impurity diffusion layer
4
before the deep impurity diffusion layer
6
is formed, thus diffusing the impurity of the shallow impurity diffusion layer
4
to a deep depth and making it difficult to form the aimed shallow impurity diffusion layer.
In order to solve this problem, it is proposed to use the method of forming a deep impurity diffusion layer first after forming a gate side-wall insulating layer and then forming a shallow impurity diffusion layer after removing the side-wall insulating film (Ref. Kenichi Goto et al. “A High Performance 50 nm PMOSFET using Decaborane (B
10
H
14
) Ion Implantation and 2-step Activation Annealing Process” IEDM-97, pp. 471-474). However, this technology does not provide the gate side-wall insulating film, and therefore forms a silicide film on the side wall of the gate electrode when trying to provide a low resistance silicide film on the upper side of the gate and on the upper side of the impurity diffusion layer, resulting in a short circuit formed between the gate electrode and the impurity diffusion layer. Accordingly this structure cannot be applied to the silicide process.
Further, in this method, the side-wall insulating layer is removed by isotropic etching without covering the gate insulating film, so that an exposed portion of the gate insulating film is slightly etched. This makes the life of the gate insulating film shorter, or, at worst, a failure occurs in the gate insulating film.
BRIEF SUMMARY OF THE INVENTION
The objects of this invention are to form a shallow impurity diffusion layer adjacent to a gate electrode, to provide the method of manufacturing a MOS transistor or a MIS transistor of the silicide type improved in the short channel effect, and to provide the composition of a semiconductor device which is made possible by this method.
In order to achieve the foregoing objects, a manufacturing method of a semiconductor device, which is a first aspect of the present invention, comprising the steps of:
forming a gate electrode on a semiconductor substrate through a gate insulating film;
forming a protective insulating film on a side-wall of the gate electrode;
forming a first side-wall insulating film on the protective insulating film formed on the side-wall of the gate electrode;
forming a first impurity diffusion layer on a surface of the semiconductor substrate by using the gate electrode and the first side-wall insulating film as a mask;
removing the first side-wall insulating film after the step of forming the first impurity diffusion layer;
forming a second impurity diffusion layer on the surface of the semiconductor substrate by using the gate electrode and the protective insulating film as a mask after the step of removing the first side-wall insulating film;
forming a second side-wall insulating film on the protective insulating film formed on the side-wall of the gate electrode after the step of forming the second impurity diffusion layer; and
forming a conductive film on an upper surface of the gate electrode and on a surface of the second impurity diffusion layer by using the second side-wall insulating film as a mask.
It is desirable that the step of forming the conductive film includes the step of forming a conductive film having a resistance lower than that of the second impurity diffusion layer.
It is desirable that a thickness of the first side-wall insulating film differs from that of the second side-wall insulating film.
It is desirable that a thickness of the first side-wall insulating film is smaller than that of the second side-wall insulating film.
Material of the first side-wall insulating film can be differentiated from that of the second side-wall insulating film.
It is desirable that the material of the first side-wall insulating film is SiO
2
and that the second side-wall insulating film is composed of SiN.
It is desirable that the step of forming the first impurity diffusion layer and the step of forming the second impurity diffusion layer include the step of introducing and activating an impurity and a temperature of a heat treatment for activating the impurity of the first impurity diffusion layer is higher than that of the second impurity diffusion layer.
It is desirable that a diffusion distance of an impurity of the first impurity diffusion layer is longer than that of the second impurity diffusion layer.
It is desirable that the step of forming the first or second side-wall insulating film includes the step of forming a silicon oxide film and a silicon nitride film laminated thereon, and that the step of forming a conductive film on an upper surface of the gate electrode and on a surface of the first or second impurity diffusion layer includes the step of performing selective growth of silicon under a supply limited condition, and the step of performing selective growth of silicon under a reaction limited condition, after the step of performing selective growth of silicon under a supply limited condition.
It is also desirable to provide the step of etching back the silico

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