Process for etching conductors at high etch rates

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S710000, C438S712000, C438S714000, C438S720000

Reexamination Certificate

active

06593244

ABSTRACT:

This invention relates to a method for etching conductors at very high etch rates. More particularly, this invention relates to a high etch rate process for anisotropically etching conductors such as silicon.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor and other devices, several steps require etching of conductors such as silicon, either single crystal silicon, epitaxial silicon or polysilicon, as well as metals and metal compounds, anisotropically, at high etch rates. As an example, when making deep vertical trenches in silicon, an anisotropic etch is required; a too tapered etch profile will stop when the sidewalls converge, and any isotropic etching makes the opening difficult to fill. A fluorine-based plasma etch is convenient because high etch rates can be achieved. However, fluorine-based etchants are inherently isotropic, with the result that the sidewalls of the etched trenches are attacked, producing non-uniform sidewall profiles.
Photoresist is generally used to pattern the desired trench. When very deep trenches are to be made however, a problem arises. The etchant for silicon generally also etches the photoresist, albeit more slowly. Thus as the trench gets deeper, more photoresist is etched away as well. The silicon etch must be stopped before the photoresist pattern is removed in order to maintain the desired patterning; this frequently limits the depth of the etch. It is known to choose an etchant, such as HBr, that will deposit polymeric material on the sidewall of the etched trench to protect it and to maintain anisotropy. However, HBr is a highly corrosive etchant which can attack the walls and fixtures of the etch chamber.
Thus the present invention seeks to achieve a desired anisotropic etch of silicon at high etch rates.
SUMMARY OF THE INVENTION
The etch process of the invention employs a first fluorine-containing etch gas and a second gas that forms a polymer that can protect the photoresist and etched sidewalls. The process anisotropically etches a photoresist masked conductor substrate at very high etch rates and also obtains very high selectivity to the photoresist.
These first and second gases can be used together or sequentially. The two gases can be added to the etch chamber also alternately, in any order.
During deposition, a fluorocarbon or hydrofluorocarbon gas is passed into a plasma etch chamber at low pressure using a high source power. This deposits a fluorocarbon polymer passivation layer on the sidewalls of the photoresist pattern walls, protecting the photoresist, and on the sidewalls of the developing openings in a metal or silicon-containing layer.
Using the fluorine-containing etchant, a fluorine-containing etch gas, under conditions of high source power, high pressure and using bias power to the substrate support electrode as well, provides a very high etch rate and an anisotropic etch of silicon for example. The use of two gases, one for polymer deposition and protection of the photoresist pattern and etched opening sidewalls and the second gas for metal or silicon conductor etch, results in both high etch rates and anisotropy. In addition, the selectivity between the material etched and the photoresist is very high, generally over 70.


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Rangelow, “High resolution tri-level process by downstream RF biased etching”, SPIE vol. 1392, Advanced Techniques for Integrated Circuit Processing (1990) pp 180-184.
Tsujimoto et al, “A New Side Wall Protection Technique in Microwave Plasma Etching Using a Chopping Method”, Extended Abstracts of 18th Conf. on Solid State Devices and Materials, Bus Center Acad. Soc. Japan, 1986, pp 229-232.

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