Process for DRAM cell production

Details Process for DRAM cell production Process for DRAM cell production

1999-09-10

2001-10-02

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S245000, C438S246000, C438S700000

Reexamination Certificate

active

06297087

ABSTRACT:

BACKGROUND AND SUMMARY OF INVENTION
According to the present invention there is provided a process for DRAM cell production comprising the steps of (1) depositing a layer of a first substance in a trench, (2) depositing a first layer of a second substance in said trench, (3) growing an interfacial layer of oxide (a) between said layer of said first substance and said first layer of said second substance, and (b) between side walls of said trench and said first layer of said second substance, (4) applying an anisotropic etching substance to the surface of said first layer of said second substance, thereby protecting said interfacial layer of oxide between said side walls of said trench and said first layer of said second substance and exposing said interfacial layer of oxide disposed on top of said layer of said first substance, (5) applying a second etching substance, thereby substantially removing said interfacial layer of oxide disposed on top of said layer of said first substance, and (6) depositing a second layer of said second substance in said trench in a manner which substantially fills said trench. However, the presence of the interfacial layer of oxide also resulted in an unwanted increase in the contact resistance of the buried strap causing a production yield loss in low temperature performance cells.
The present invention solves the technical problem of reducing the contact resistance of the buried strap and thus improving the production yield for low temperature performance cells.
According to the present invention there is provided a process for DRAM cell production comprising the step of depositing a layer of a first substance in a trench, characterised in that said process further comprises the steps of depositing a first layer of a second substance in said trench, growing an interfacial layer of oxide between said layer of said first substance and said first layer of said second substance, and between side walls of said trench and said first layer of said second substance, applying an anisotropic etching substance to the surface of said first layer of said second substance, thereby protecting said interfacial layer of oxide between said side walls of said trench and said first layer of said second substance and exposing said interfacial layer of oxide and said first layer of said second substance disposed on top of said layer of said first substance, applying a second etching substance to the surface of said first layer of said second substance, thereby substantially removing said interfacial layer of oxide and said first layer of said second substance disposed on top of said layer of said first substance, and depositing a second layer of said second substance in said trench in a manner which substantially fills said trench.
Said layer of said first substance may be approximately 300 nm thick and said first substance may be arsenic doped phosphorous silicon.
Said first layer of said second substance may be approximately 50 nm thick and said second substance may be silicon.
Said interfacial layer of oxide may be approximately 2 nm thick.
Said second layer of said second substance may be approximately 250 nm thick.
Said anisotropic etching substance may be a substance comprising hydrochloric acid, chlorine, and helium oxide (HCL, CL
2
, He/O
2
).
Said second etching substance may be hydrofluoric acid (HF).
As will be appreciated by those skilled in the art various types of silicon may be used such as arsenic doped boron silicon and the thickness of the layers may be varied. Furthermore, as will be appreciated, other types of etching substances may be used in this process, such as hydrofluoric acid containing vapour.
The present invention provides an improvement to existing DRAM production processes by maintaining protection against dislocation through the use of an interfacial layer of oxide on the side walls of the trenches, while reducing the unwanted contact resistance caused by the presence of the interfacial layer of oxide between the two layers of silicon. By reducing the contact resistance the DRAM cell is less prone to failure during low temperature operation. Thus the present invention provides a higher production yield for low temperature performance cells.


REFERENCES:
patent: 4824793 (1989-04-01), Richardson
patent: 5677219 (1997-10-01), Mazure' et al.
Ssato et al., “Transistor on Capacitor (TOC) Cell with Quarter Pitch Layout for DRAM”, IEEE,ED 45, pp. 82,83, 1998.

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