Process for device isolation

Details Process for device isolation Process for device isolation

2002-01-09

2002-12-03

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S412000, C438S432000, C438S442000

Reexamination Certificate

active

06489193

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to semiconductor manufacturing. In particular, the present invention relates to a process for isolating devices on a semiconductor substrate.
2. Description of the Related Arts
Integrated circuits are formed from semiconductor substrates, usually silicon (Si), within and upon whose surfaces are formed active semiconductor regions containing electrical circuit elements that are internally and externally connected to the substrate through multiple patterned conductor layers that are separated by dielectric layers. These active semiconductor regions must be otherwise electrically isolated from adjacent active semiconductor regions by the formation of intervening trenches which are subsequently filled with dielectric material to ensure such electrical isolation and avoid undesired interference between adjacent active semiconductor regions. The continued miniaturization of integrated circuit devices has resulted in smaller trenches formed by, for example, shallow trench isolation (STI) methods to form trench isolation regions essentially co-planar with adjacent active semiconductor regions of the semiconductor substrates.
However, for these increasingly miniaturized integrated circuits with corresponding miniaturized shallow isolation trenches, an undesired void, or keyhole, is formed within the gap filling silicon oxide layer within the trench. It is easy to form an overhead at the top corners of shallow trenches using traditional CVD-ox (chemical vapor deposition of silicon oxide) to gap filling and thus voids are formed. As shown in
FIG. 1
, a common problem associated with trench refill isolation is the formation of voids in the trenches. During refill of the trench
140
with dielectric material
160
, the trench
140
often becomes constricted near the top of the trench, thereby preventing complete refill of the trench, resulting in a void
200
. Void defects may trap contamination or make the final oxide surface of the STI (shallow trench isolation region) lower than the active surface. Also, junction leakage would increase. Increasing the trench width can alleviate void formation, however, it also undesirably decreases device density.
Accordingly, a need exists for a novel device isolation technique that allows high density integrated circuits to be fabricated with improved reliability.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a novel isolation process which overcomes the problem of void formation while providing effective device isolation.
To achieve the above and other objects, the present invention provides a novel isolation process where isolation regions are formed by depositing a blanket isolation layer over a semiconductor substrate and patterning the isolation layer, as opposed to the conventional trench isolation process where the isolation regions are formed by refilling isolation trenches. Thereby, the problem of void formation can be avoided. According to another feature of the invention, after forming the isolation regions, a semiconductor layer is provided between two isolation regions to serve as an active region where semiconductor devices are to be formed. In other words, semiconductor devices will be fabricated on the newly formed semiconductor layer instead of original substrate surface.
According to an aspect of the invention, there is provided a process for isolating devices on a semiconductor substrate, comprising the steps of forming an isolation layer over the semiconductor substrate; patterning the isolation layer into at least two isolation mesas; forming a semiconductor layer over the substrate with a thickness sufficient to cover the isolation mesas; and planarizing the semiconductor layer until the isolation mesas are exposed, whereby leaving a semiconductor region between the two isolation mesas to serve as an active region for semiconductor devices.
According to another aspect of the invention, there is provided a process for isolating devices on a semiconductor substrate, comprising the steps of forming an isolation layer over the semiconductor substrate; forming a photoresist layer over the isolation layer; patterning the photoresist layer to provide a mask that is substantially the reverse of predetermined active regions to be formed; anisotropically etching the isolation layer with the patterned photoresist layer as an etch mask, thereby forming a plurality of isolation mesas; removing the photoresist layer; forming a semiconductor layer over the substrate with a thickness sufficient to cover the isolation mesas; and planarizing the semiconductor layer until the isolation mesas are exposed, thereby leaving a plurality of semiconductor regions separated by the isolation mesas to serve as active regions for semiconductor devices.


REFERENCES:
patent: 4910165 (1990-03-01), Lee et al.
patent: 5893745 (1999-04-01), Park
patent: 6048765 (2000-04-01), Wu
patent: 6153467 (2000-11-01), Wu
patent: 6162689 (2000-12-01), Kepler et al.

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