Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-07-29
2002-06-18
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S582000, C438S592000, C438S649000, C438S651000, C438S682000, C438S683000, C438S201000
Reexamination Certificate
active
06406952
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to fabrication of integrated circuits.
2. Discussion of the Related Art
A variety of applications utilize CMOS (Complimentary Metal Oxide Semiconductor) integrated circuits. Many CMOS integrated circuits contain a dual-gate structure, illustrated in part by FIG.
7
. Typically, formation of a dual-gate structure begins by forming a gate dielectric region
108
over a silicon substrate
100
having an n-doped region
102
and a p-doped region
104
. (A dielectric material is an electrically insulating material, i.e., a material having a resistivity of about 10
6
ohm-cm or greater.) A field dielectric
106
is also formed to isolate the oppositely-doped regions of the device. A polysilicon region
110
is typically deposited over the gate dielectric
108
and field dielectric
106
. The portion of the polysilicon
110
overlying the n-doped region
102
is provided with a p-type dopant such as boron or BF
2
, and the portion of the polysilicon
110
overlying the p-doped region
104
is provided with an n-type dopant such as phosphorus or arsenic. Such dual-gate CMOS configurations typically contain a refractory metal silicide layer
112
(or other metal layer) over the doped polysilicon, the refractory metal silicide acting to lower resistance in the gate structure and thereby improve device and circuit performance.
However, n-type and p-type dopants tend to diffuse more readily in refractory metal silicides than in polysilicon. Dopants thus tend to diffuse, for example, from a region of the polysilicon
110
overlying doped silicon region
102
into the suicide layer
112
, laterally in the silicide layer
112
, and then back into the polysilicon
110
at a region overlying the oppositely-doped region
104
. Thus, n-type dopants move into a p-doped polysilicon region and vice versa. The phenomenon is referred to herein as cross-doping. Diffusion of these cross-dopants into the area of the polysilicon adjacent to the underlying gate dielectric causes undesirable shifts in threshold voltage, an important parameter in CMOS design and operation. Moreover, the problem of cross-doping is becoming more severe as the industry moves toward smaller CMOS devices, e.g., moving towards 0.25 &mgr;m length devices, and even more significantly toward 0.18 &mgr;m and lower. The smaller the devices, the larger the effect of cross-dopants on properties such as threshold voltage, and the closer the devices, the less distance the dopants have to laterally travel to interfere with adjacent devices.
Problems are also created by the distribution of dopants in the implanted regions of the polysilicon
110
. Advantageously, the implanted dopants in the final device are located near the underlying gate dielectric
108
. Typically, however, the majority of dopants lie close to the top of the polysilicon
110
, and an anneal is used to diffuse the dopants toward the gate dielectric
108
. However, the anneal time and temperature required to diffuse the dopants across this distance will often undesirably allow diffusion of some of the dopants laterally within the polysilicon
110
into an oppositely-doped region of the polysilicon
110
, causing cross-doping. This lateral diffusion within the polysilicon
110
is a problem regardless of whether a silicide layer is present. This mechanism of cross-doping is particularly problematic where half the distance between the active regions of adjacent devices becomes comparable to the thickness of the doped regions of the polysilicon
110
. In addition, the use of thinner gate dielectric layers improves device performance, but only where a relatively large concentration of dopants, advantageously about 10
20
dopants/cm
3
or greater, is located adjacent to the gate dielectric (resulting in what is known in the art as low poly-depletion). If sufficient dopants are not located adjacent to the dielectric layer, the use of a thinner gate dielectric will at best only marginally improve device performance.
It is also possible for dopant distribution to cause problems when forming a refractory metal silicide by a salicide process. In a typical salicide process, a refractory metal is deposited after formation of a polysilicon gate structure, a source and drain, and silicon dioxide spacers. The device is heated to react the metal with the silicon, thereby forming a refractory metal silicide. Due to a low level of bonding between the refractory metal and the silicon dioxide spacers, the silicide typically does not form on the spacers, leading to what is conventionally known as self-alignment of the silicide structure. Growth of the silicide layer in such a salicide process is detrimentally affected if too many dopants, or dopant-based precipitates, are located in the top region of the polysilicon gate structure, where the silicide is formed. In addition, because the polysilicon region is typically thicker when using a salicide process, the dopant diffusion distance to the gate dielectric is often increased, thereby allowing encroachment of the underlying channel region that often leads to shorts in the device.
For these reasons, a process that places dopants deep within the polysilicon layer is desired. Such a deep implant is difficult to attain, however. Typically, as mentioned above, the majority of dopants will lie close to the top surface of the polysilicon regions. It is difficult to implant dopants deeper in the polysilicon without encountering undesirable effects. For example, it is possible for dopants, particularly boron, to penetrate the polysilicon during ion implantation and move into the underlying silicon substrate, or to move along certain crystallographic orientations of polysilicon—a phenomenon known as channeling. (Both mechanisms are referred to herein generally as penetration.) The presence of the boron in the channel region of the silicon substrate detrimentally affects the threshold voltage. Thus, implantation is performed at energies low enough to reduce penetration. Yet, where lower implantation energies are used, the concentration profile will often not be deep enough to avoid the problems discussed above.
Thus, improved processes which address problems created by cross-doping and by certain dopant concentration profiles, particularly in smaller, dual-gate CMOS devices, are desired.
SUMMARY OF THE INVENTION
The process of the invention addresses problems of cross-doping, and of undesirable dopant concentration profiles, found in current CMOS fabrication processes, and is also applicable to smaller devices. In an embodiment of the invention, devices are prepared by forming a first, relatively thin (e.g., about 300-1000 Å) amorphous silicon region over a gate dielectric material region formed over n-type and p-type regions of a silicon substrate. It is also possible to use polysilicon. (The term amorphous indicates a lack of long-range order.) An n-type dopant is implanted at a first portion of the first amorphous silicon region, typically over the p-type region of the substrate. The n-type dopant is advantageously implanted such that substantially all of the dopant remains in the first amorphous silicon region and does not penetrate into the underlying dielectric region or the substrate. “Substantially all” indicates that no more than about 0.001% of the implanted dopant penetrates into the underlying dielectric layer or substrate during implantation. This result is attained, for example, by use of a low energy ion implantation method, e.g., implanting arsenic at 2-30 keV or phosphorus at 1-20 keV. A p-type dopant species is then implanted at a second portion of the first amorphous silicon region, typically over the n-type region of the substrate. Again, it is advantageous for substantially all of the p-type dopant species to remain in the first amorphous silicon region. It is possible for this result to be similarly attained by use of low energy ion implantation, e.g., implanting boron at 0.25-5 keV.
Once the desired dopants are implanted into the first silicon regio
Agere Systems Guardian Corp.
Brairton Scott
Pham Long
Rittman Scott J.
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