Process for depositing a stratified dielectric structure for enh

Details Process for depositing a stratified dielectric structure for enh Process for depositing a stratified dielectric structure for enh

1997-12-23

1999-11-30

Utech, Benjamin

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438778, 438723, 438787, H01L 214763

Patent

active

059942312

ABSTRACT:
A method of depositing a layered dielectric structure to improve the planarity of electronic devices which include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. The bit lines are isolated from one another by a layered dielectric structure to provide a planar architecture onto which an optional conductive layer may be deposited. The dielectric structure is formed from a highly planarizing dielectric layer of the SOG type spun over a first insulating dielectric layer and solidified by means of a thermal polymerization process. After solidifying the dielectric layer, it is subjected to a rapid thermal annealing treatment.

REFERENCES:
patent: 5290399 (1994-03-01), Reinhardt
patent: 5554567 (1996-09-01), Wang
patent: 5618757 (1997-04-01), Bothra et al.
patent: 5679211 (1997-10-01), Huang
patent: 5681425 (1997-10-01), Chen
patent: 5747381 (1998-05-01), Wu et al.
Patent Abstracts of Japan for Patent #JP04030524 published Feb. 3, 1992 at vol. 16, No. 200, May 13, 1992.
"Spin-on Glass Curing by Rapid Thermal Annealing," Journal of the Electrochemical Society, vol. 137, No. 12, pp. 3923-3925, Dec. 1, 1990.

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