Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-08-04
2004-06-22
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S758000, C438S782000, C438S787000, C438S789000, C438S790000
Reexamination Certificate
active
06753270
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the formation of dielectric layers during fabrication of integrated circuits on semiconductor wafers. More particularly, the present invention relates to a method for providing a dielectric film having a low dielectric constant that is particularly useful as an intermetal dielectric layer.
One of the primary steps in the fabrication of modem semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition or “CVD.” Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having metal layers.
One particular thermal CVD process that has been developed to deposit insulation films over metal layers at relatively low, non-damaging temperatures includes deposition of a silicon oxide layer from TEOS and ozone precursor gases. Such a TEOS/ozone silicon oxide film may be deposited under carefully controlled pressure conditions in the range of between about 100-700 Torr, and is therefore commonly referred to as a sub-atmospheric CVD (SACVD) film. The high reactivity of TEOS with ozone reduces the external energy required for a chemical reaction to take place, and thus lowers the required temperature for such SACVD processes.
Another CVD method of depositing silicon oxide layers over metal layers at relatively low temperatures includes plasma enhanced CVD (PECVD) techniques. Plasma enhanced CVD techniques promote excitation and/or dissociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone proximate the substrate surface. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such PECVD processes.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. As devices become smaller and integration density increases, issues that were not previously considered important by the industry are becoming of concern. With the advent of multilevel metal technology in which three, four, or more layers of metal are formed on the semiconductors, one goal of semiconductor manufacturers is lowering the dielectric constant of insulating layers such as intermetal dielectric (IMD) layers. Low dielectric constant films are particularly desirable for IMD layers to reduce the RC time delay of the interconnect metalization, to prevent cross-talk between the different levels of metalization, and to reduce device power consumption.
In order to visualize the multiple IMD layers in an integrated circuit,
FIG. 1
illustrates a simplified cross-sectional view of an exemplary integrated circuit
100
. As shown in
FIG. 1
, integrated circuit
100
includes NMOS and PMOS transistors
103
and
106
, which are separated and electrically isolated from each other by a field oxide region
120
. Each transistor
103
and
106
comprises a source region
112
, a gate region
115
and a drain region
118
.
A pre-metal dielectric (PMD) layer
121
separates transistors
103
and
106
from metal layer M
1
with connections between metal layer M
1
and the transistors made by contacts
124
. In this exemplary integrated circuit
100
, metal layer M
1
is one of four metal layers, M
1
-M
4
. Each metal layer M
1
-M
4
is separated from adjacent metal layers by respective intermetal dielectric layers
127
(IMD
1
, IMD
2
and IMD
3
). IMD layers
127
may include a PECVD lining layer
130
, an ozone/TEOS SACVD gap fill layer
133
and a cap layer
136
. Adjacent metal layers are connected at selected openings by vias
126
. Deposited over metal layer M
4
are planarized passivation layers
140
.
It is known that the properties of the SACVD gap fill layer
133
depend on the underlying surface onto which it is deposited. When the SACVD layer is deposited over a silicon oxide layer, such as the steam oxide or PECVD lining layer, or on the surface of a metal, the quality of the SACVD layer generally deteriorates because of surface sensitivity. The quality of such an SACVD silicon oxide layer is not as good as the quality of “steam oxide” grown on the surface of a silicon substrate by heating the substrate in the presence of steam. For example, the CVD layer is less stable than steam oxide and tends to absorb moisture over time. Such moisture absorbtion increases the dielectric constant of the layer and may lead to outgassing problems when the film is heated during subsequent processing steps.
The surface sensitivity of the SACVD layer is manifested by an increase of the wet etch rate compared to the wet etch rate of thermally grown steam oxide and a decrease of the deposition rate and a rougher surface morphology as compared to the deposition rate and surface morphology of an SACVD layer deposited directly on a silicon substrate. The wet etch rate ratio (WERR) is the ratio of the wet etch rate of an SACVD layer deposited over the PECVD lining layer to the wet etch rate of a thermally grown steam oxide. The CVD layer is typically more porous than a steam layer and tends to etch away more quickly than the steam oxide. The deposition rate w ratio (DRR) is the ratio of the deposition rate of the SACVD layer deposited over the PECVD lining layer to the deposition rate of an SACVD layer deposited directly on a bare silicon substrate. Thus, surface sensitivity is manifested by a high WERR and a low DRR.
Generally, surface sensitivity has been recognized to be undesirable in the industry. Accordingly, various techniques have been developed within the industry to reduce the sensitivity of the SACVD layer of a two-layer silicon oxide gap filling film. For example, one well-known method, developed at Applied Materials, Inc., treats the PECVD lining layer with an N
2
plasma excited by mixed RF frequencies (13.56 MHz and 350 KHz) prior to deposition of the SACVD layer.
Undoped silicon oxide films, such as the combination SACVD gap fill/PECVD lining layer just described, may have a dielectric constant as low as about 4.0 or 4.2. While depositing an SACVD gap fill layer over a reduced surface sensitivity PECVD lining layer is one commercially successful approach used to form IMD layers, approaches to obtain lower dielectric constant films for IMD layers
127
have been and still are being explored.
One approach to obtaining a lower dielectric constant is to incorporate fluorine in the silicon oxide film. Fluorine-doped silicon oxide films (also referred to as fluorine silicate glass or —“FSG” films) may have a dielectric constant as low as about 3.4 or 3.6. Despite this improvement, films having even lower dielectric constants (e.g., about 3.2 or less) are highly desirable for the manufacture of integrated circuits using geometries of 0.18 &mgr;m and smaller. Numerous films have been developed in attempts to meet these needs including: a spin-on glass called HSQ (hydrogen silsesqui-oxane, HSiO
1.5
) and various carbon-based dielectric layers. While the above types of dielectric films are useful for some IMD applications, manufacturers are always seeking new and improved methods of depositing low-k materials for use as IMD and other types of dielectric layers.
SUMMARY OF THE INVENTION
The methods of the present invention provides such a new and improved low-k material deposition process. The process is particularly useful in the manufacture of sub-0.2 micron circuits as it can form an IMD film with a dielectric constant of about 3.2 and below. The film has good gap fill capabilities and high film stability. Furthermore, the film is deposited from constituent gases that have been used by semiconductor manufacturers to deposit other dielectric layers. Thus, the film is easily integrated into established manufacturing processes.
The method of the present invention de
Gaillard Frederic
Geiger Fabrice
Applied Materials Inc.
Cuneo Kamand
Kilday Lisa
Townsend & Townsend & Crew
LandOfFree
Process for depositing a porous, low dielectric constant... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for depositing a porous, low dielectric constant..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for depositing a porous, low dielectric constant... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3342718