Process for defining ultra-thin geometries

Details Process for defining ultra-thin geometries Process for defining ultra-thin geometries

1998-06-16

2001-05-01

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S303000, C438S304000, C438S585000, C438S692000, C438S947000

Reexamination Certificate

active

06225175

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to procedures for accurately defining very small geometries, on the order of down to about 50 angstroms, in the fabrication of semiconductor devices.
2. Brief Description of the Prior Art
As the geometries of semiconductor devices become increasingly smaller, photolithographic techniques are becoming increasingly less capable of coping with the requirement to accurately define the geometry of gate lengths and contact openings in the fabrication of such devices. This problem is particularly acute when viewed from an economic perspective. Accordingly, there is a continuing effort in the art of semiconductor fabrication to resolve this problem and the present invention is a continuation of this effort.
It is known that the geometries of sidewall depositions can be very closely controlled on an economic basis in view of the fact that the sidewall thicknesses can be very well controlled down to thicknesses in the tens of angstroms. The formation and use of sidewall oxides in particular have been well known in the art for many years. It is also known in the prior art to use sidewall spacers on the gates of MOSFETs to separate the source/drain implant from the channel region and to separate the source/drain silicide from the gate silicide. It is further known to use sidewall layers to form narrow gate structures.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a procedure for accurately and repeatedly providing ultra-thin component geometries which can be as thin as about 50 angstroms and which can optionally also provide self alignment to another feature of the device being fabricated using the known properties and control of sidewalls, both in the form of permanent materials as well as materials intended to be removed during processing.
The fabrication of semiconductor devices is accomplished in accordance with the present invention using the properties of sidewall depositions as known in the prior art. Briefly, a sidewall disposition is formed which may or may not be a permanent part of the final device. The material from which the sidewall is formed can be any material which is capable of being removed selective to material which surrounds or will surround the sidewall either entirely or in part, which is substantially inert to other fabrication steps as long as it is present and which is sufficiently rigid to operate as a mask and/or as a permanent part of the final device being fabricated. The sidewall is formed to the desired thickness, such formation being capable of accuracy to within about 0.1 nanometer and down to thicknesses of about 50 angstroms. A material other than that of the sidewall is then deposited adjacent the sidewall and the surface against which the sidewall is disposed, the sidewall and the newly deposited material are planarized, such as by chemical-mechanical polishing (CMP) to expose the top of the sidewall layer for subsequent processing (e.g., siliciding or making contact thereto). Subsequently, either the remaining sidewall or the material surrounding the remaining sidewall may be removed by use of an etchant or etchants selective to either the sidewall material or the material surrounding the sidewall material. The end result is either an aperture or slot where the sidewall was formed, the free-standing sidewall or the sidewall and surrounding material with coplanar outer surfaces. In either case, the dimensions of the aperture or sidewall are accurately controlled down to dimensions less than 0.1 nanometer and generally down to about 50 angstroms.


REFERENCES:
patent: 5846857 (1998-12-01), Ju
Dudek et al, Lithography-Independent Nanometer Silicon MOSFET on Insulator, IEEE. No month 1996.*
“An Ultra Low Power Lateral Bipolar Polysilicon Emitter Technology on SOI”, Dekker et al., 1999 IEEE, pp 75-77, no month 1993.
“Lithography-Independent Namoneter Silocon MOSFET's on Insulator”, Dudek et al., vol. 43. No. 10, Oct. 1996, pp. 1626-1631.
“A Novel High-Performance Lateral Bipolar on SOI”, Shahidi et al., 1991 IEEE, pp 663-666, no month.

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