Process for controlling the read amplifiers of a memory and...

Details Process for controlling the read amplifiers of a memory and... Process for controlling the read amplifiers of a memory and...

2006-05-23

2006-05-23

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S204000, C365S205000

Reexamination Certificate

active

07050348

ABSTRACT:
An integrated circuit includes a memory, and the memory includes a memory plane arranged in rows and columns, and a plurality of read amplifiers connected to the columns of the memory plane. A reference path includes first and second reference columns, and a reference memory cell is connected between the first and second reference columns. A reference row is connected to the reference memory cell for selection thereof so that the first reference column conducts a discharge current and the second reference column conducts a leakage current. A control circuit is connected between the first and second reference columns and the read amplifiers. The control circuit provides an activation signal to the read amplifiers when an absolute value of a difference between voltages on the first and second reference columns exceeds a threshold.

REFERENCES:
patent: 4056811 (1977-11-01), Baker
patent: 5699295 (1997-12-01), Yero
patent: 5742552 (1998-04-01), Greenberg
patent: 6055187 (2000-04-01), Dallabora et al.
patent: 6434068 (2002-08-01), Harada et al.
patent: 6512697 (2003-01-01), Li et al.
patent: 2002/0080670 (2002-06-01), Kawasumi
patent: 2002/0186579 (2002-12-01), Yokozeki

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