Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-20
2002-09-17
Fahmy, Wael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S248000, C438S386000, C438S391000, C438S424000
Reexamination Certificate
active
06451648
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor devices. In particular, the present invention relates to dynamic random access memory (DRAM) devices.
BACKGROUND OF THE INVENTION
Increasing numbers of semiconductor devices, such as individual memory cells, are being created on a single chip. As a result, dimensions of the devices continue to shrink. Shrinking device dimensions can increase the difficulty of and errors aligning device structures and the difficulty of ensuring proper alignment an adequate functional area of structures included in semiconductor devices.
SUMMARY OF THE INVENTION
The present invention provides a method and semiconductor device structure for helping to ensure proper alignment of elements of semiconductor device structures in light of the increasingly reduced dimensions of semiconductor devices and elements forming the devices.
The present invention provides a process for forming a buried strap self-aligned to a deep storage trench. According to the process, spacers are formed on walls of a recess over a filled deep trench capacitor and a substrate. A plug is formed in a region between the spacers. Photoresist is deposited over the spacers, the plug, and material surrounding the spacers of the plug. The photoresist is patterned, thereby exposing portions of the plug, the spacers, and the surrounding material. The spacers in the surrounding material not covered by the photoresist are selectively etched, leaving a remaining portion of the spacers. The portion of the substrate not protected by the photoresist is selectively etched. An isolation region is formed in a space created by the etching of the spacers and substrate.
The present invention also provides a semiconductor device including a substrate. A deep trench capacitor is arranged in the substrate. The deep trench capacitor is filled with a semiconductor material. A collar is arranged on the wall of the deep trench. A trench top region is arranged in the vicinity of a top of the trench over the trench fill and the collar. An isolation region extends into the deep trench, the trench collar, and the trench top region.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5395786 (1995-03-01), Hsu et al.
patent: 5525531 (1996-06-01), Bronner et al.
patent: 5614431 (1997-03-01), DeBrosse
patent: 11074474 (1999-03-01), None
patent: 411168203 (1999-06-01), None
IBM Technical Disclosure Bulletin, vol. 33, No. 10A, Mar. 1991, “Process Scheme to Make Shallow Trench Isolation Self-Aligned to the Storage Trench” pp. 260-262.
Gruening Ulrike
Radens Carl J.
C. Li Todd M.
Connolly Bove & Lodge & Hutz LLP
Fahmy Wael
Neff Daryl K.
Thomas Toniae M.
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