Process flow for a performance enhanced MOSFET with...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S270000, C438S243000, C438S421000, C257S330000, C257S301000, C257S396000

Reexamination Certificate

active

07091092

ABSTRACT:
A method for forming a self-aligned, recessed channel, MOSFET device that alleviates problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A thin pad oxide layer is grown overlying the substrate and a gate recess, followed by deposition of a thick silicon nitride layer filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown, thickening the pad oxide layer. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is removed. The oxide layer at the bottom of the gate recess is removed and a gate dielectric layer is grown. Gate polysilicon is deposited filling the gate recess. S/D implantations, metallization, and passivation complete fabrication of the device.

REFERENCES:
patent: 5270228 (1993-12-01), Ishikawa
patent: 5599728 (1997-02-01), Hu et al.
patent: 5610090 (1997-03-01), Jo
patent: 5814544 (1998-09-01), Huang
patent: 6358800 (2002-03-01), Tseng

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