Process fabricating semiconductor device having two ion-implanta

Details Process fabricating semiconductor device having two ion-implanta Process fabricating semiconductor device having two ion-implanta

1997-05-28

1998-12-29

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438276, H01L 218234

Patent

active

058541101

ABSTRACT:
A semiconductor read only memory device has a p-type contact region nested in a p-type drain region of a p-channel type field effect transistor and formed through a first ion-implantation of boron through a first opening of a photo-resist mask and a first contact hole of an inter-level insulating layer under a first acceleration energy too small to penetrate the inter-level insulating layer and a channel region of a memory transistor formed in a p-type well and formed through a second ion-implantation of phosphorous through a second opening of the photo-resist mask and the inter-level insulating layer under a second acceleration energy too large to stop the phosphorous in the p-type drain region so that the photo-resist mask is shared between the two ion-implantations.

REFERENCES:
patent: 5156989 (1992-10-01), Williams et al.
patent: 5242841 (1993-09-01), Smayling et al.
patent: 5449637 (1995-09-01), Saito et al.

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