Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-03
2001-08-14
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S676000, C438S679000, C438S761000, C438S763000
Reexamination Certificate
active
06274492
ABSTRACT:
The invention relates to a process and a device for the metallisation of semiconductor structures by which regions of the surface can be electrically connected by means of strip conductors in one or several planes and contacts between the strip conductors of different planes. With the increasing density and complexity on the chip the requirements of the metal coating process continuously grow. Ever-increasing numbers of strip conductors on the different planes and contacts between the strip conductors have to be realized. Strip conductors of ever-decreasing widths and contact areas are used. The structural fineness following for the metallisation of the VLSI components demands specially adapted processes.
In some processes the material of the strip conductors is coated on the whole surface of the plane substrates. Structuring is by back etching and use of masks. In other processes the strip conductor and contact material is coated on substrates whose surface has previously been provided with the trenches and holes necessary for strip conductors and contacts. A subsequent, for example, CMP process removes the undesired conducting material outside of the trenches and holes. In this process the conforming deposition of an adhesion and barrier coating on the surface of the trenches and holes and subsequent filling of the trenches and holes is particularly difficult. This is due to the continuously decreasing structural widths connected with simultaneously increasing aspect ratios. Some processes use CVD processes. U.S. Pat. No. 4,900,695, for example, uses physically supported CVD processes. In general, the technological realization of CVD processes is expensive and process conduction is not without its problems in terms of environment protection. In U.S. Pat. No. 5,108,951, metallisation is carried out at higher temperatures and smaller deposition rates thus utilizing the higher mobility of the atoms of the coating material to completely fill the trenches and holes. This method, however, is unfavourable due to its low efficiency and limitation to small aspect ratios. DE 3925603 describes the production of narrow strip conductors on a relatively plane substrate by anisotropic etching of the conductive material deposited on the whole surface at a previously generated stop. A drawback is the necessity to perform a second process step, anisotropic etching. According to U.S. Pat. No. 5,401,675 a barrier for large aspect ratios is created by sputtering using a collimator. It is a disadvantage of this method that the inhomogeneity and inefficiency increase with increasing aspect ratio. The latter is particularly true for filling up with conductive material. Also known is the application of post-ionisation of the sputtered metal atoms in a plasma produced by a high-frequency field, with inductive coupling of the high-frequency field (S. M. Rossnagel and J. Hopwood, Journ. Vac. Sci. Technol. B 12 (1), January/February 1994, pp. 449-453). According to U.S. Pat. No. 5,302,266, post-ionisation of metal atoms by ECR plasmas make possible the filling of structures with large aspect ratios. These methods appear to require great effort in apparatus. Differing from the above PVD processes, according to G. A. Dixit, W. Y. Hamamoto, M. K. Jain, L. M. Ting, R. H. Havemaim, C. D. Dobson, A. I. Jeffryes, P. J. Holverson, P. Rich, D. C. Butler and J. Hems, SEMICONDUCTOR INTERNATIONAL; August 1995, pp. 79-85 the formation of cavities during filling of structures with large aspect ratios using conventional sputter coating is accepted. At a subsequent process step the cavities in the interior are eliminated using a high-pressurised inert gas and high temperature acting on the closed surface of the coated semiconductor structure. A drawback is the necessity of two process steps demanding highly different technological equipment.
It is the objective of the invention to fill the trenches and holes generated on previously structured planar microelectronic substrates in order to connect regions of the surface in one or several planes. The above disadvantages of known processes and devices are to be eliminated.
According to the invention, the problem is solved using a process given by claim
1
. Claim
2
presents an advantageous variation of the process. Further, the problem is solved by a device with the features of claim
3
. The subclaims present other useful developments of the invention.
It was found that, surprisingly, a barrier and/or low-impedance strip conductor material can be deposited from the vapour phase of a known per se pulsed vacuum arc evaporator in trenches produced for the strip conductors and holes for strip conductor connections in the substrate material such as, for example, SiO
2
or other inorganic or organic materials.
The high degree of ionisation and the high particle energy allow both the necessarily conforming coating with barrier material and subsequent filling with conductive material of the trenches and holes for large aspect ratios. The barrier layers are characterised by a low defect density. Other features of the invention for the formation of a barrier layer are the inflow of inert gases such as argon, and/or reactive gases such as nitrogen, into the recipient so that a largely conforming deposition and the desired composition of the layer are achieved. The arrangement of the substrate surface normal, parallel or inclined to the propagation direction of the plasma leads to a highly differing deposition results inside and outside of the structure. Conforming deposition can be promoted for parallel or inclined arrangement by rotating the substrates.
Another possibility to produce barriers is the arrangement of an aperture between substrate and pulsed vacuum arc evaporator. Apart from good conformity droplet-free deposition is achieved. Biasing the substrate, or substrate and aperture, respectively, effectively enhances the deposition conditions for the barrier and strip conductor materials.
A coil that produces a magnetic field axial to the pulsed vacuum arc evaporator enlarges, in connection with a biased inner surface of the coil, the efficiency and lowers the droplet proportion on the substrate. Simultaneously the conditions for filling up trenches and holes with large aspect ratios are improved.
Another possibility to lower the droplet proportion is a pulsed vacuum arc evaporator and a coil for the adjustment of the plasma characteristics to a subsequent torus coil the inner surface of which is biased. Another coil enables the torus exit to be adjusted to the substrate with structures of a large aspect ratio.
For extremely high aspect ratios, the metallisation is carried out at higher substrate temperatures typical to the material or a subsequent second step eliminates or reduces, respectively, the isolated cavities by high inert gas pressures applied onto the substrate surface, combined with appropriate high temperatures.
The advantage of the solution according to the invention is that largely droplet-free, dense, metallic coatings can be deposited on microstructured substrates with large aspect ratios. Dependent upon the process conduction the complete filling up of trenches with an aspect ratio >1 as well as the contour-conforming deposition of barrier coatings is possible.
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Klimes Wolfgang
Schultrich Bernd
Shuelke Thomas
Siemroth Peter
Urbansky Norbert
Goodwin David
Jordan and Hamburg LLP
Technische Universitaet Dresden
Wilczewski Mary
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