Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
1999-09-30
2001-08-28
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
Reexamination Certificate
active
06281029
ABSTRACT:
RELATED PATENT DOCUMENTS
The present application is related to co-pending patent documents identified by patent application Ser. No. 09/383,790, Ring et al., filed on Aug. 26, 1999, entitled “ARRANGEMENT AND METHOD FOR CHARACTERIZATION OF FIB INSULATOR DEPOSITION”; patent application Ser. No. 09/247,002, filed on Feb. 8, 1999, entitled “TEST ARRANGEMENT AND METHOD FOR A THINNED FLIP CHIP IC”; patent application Ser. No. 09/409,989, filed on Sep. 30, 1999, entitled “PROBE GRID FOR INTEGRATED CIRCUIT ANALYSIS”; and patent application Ser. No. 09/409,089, filed on Sep. 30, 1999, entitled “PROBE GRID FOR INTEGRATED CIRCUIT EXCITATION” which are assigned to the assignee of the present invention and are incorporated herein by reference.
FIELD OF THE INVENTION
The invention relates to semiconductor device assemblies, and more particularly to techniques for analyzing and debugging circuitry as may be applied, for example, to a flip-chip bonded integrated circuit.
BACKGROUND OF THE INVENTION
In recent years, the semiconductor industry has seen tremendous advances in technology, which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
In the past, the die and package were first attached and then the electrical connections from the die to the package were made by wire bonding. The wire bonding procedure is simple in concept. A thin (0.7 to 1.0 mil) wire is first bonded to the chip bonding pad and spanned to the inner lead of the package lead frame. The third action was to bond the wire to the inner lead. Lastly, the wire is clipped and the entire process repeated at the next bonding pad. While simple in concept and procedure, wire bonding was critical because of the precise wire placement and electrical contact requirements. In addition to accurate placement, each and every wire must make a good electrical contact at both ends, span between the pad and the inner lead in a prescribed loop without kinks, and be at a safe distance from neighboring lead wires.
To increase the number of pad sites available for a die and to address other problems, a different chip packaging technique called controlled collapse chip connection or flip chip packaging is being adopted. In this technology, the bonding pads are provided with metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connection to the package is made when the die is flipped over the package with corresponding bonding pads and soldered. As a result, the dies are commonly called flip chips in the industry. Each bump connects to a corresponding package inner lead. The packages that result are lower profile and have lower electrical resistance and a shortened electrical path. The output terminals of the package may be ball-shaped conductive bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. These packages are occasionally referred to as “Ball Grid Array” (BGA). Alternatively, the output terminals of the package may be pins, and such a package is commonly known as pin grid array (PGA) package.
Once the die is attached to the package, the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer of which the die is singulated from. The side of the die including the epitaxial layer containing the transistors and the other active circuitry is often referred to as the circuit side of the die or front side of the die. The circuit side of the die is positioned very near the package. The circuit side opposes the back side of the die. Between the back side and the circuit side of the die is single crystalline silicon. The positioning of the circuit side provides many of the advantages of the flip chip. However, in some instances the orientation of the die with the circuit side face down on a substrate may be a disadvantage or present new challenges. When a circuit fails, when circuit testing is desired, or when it is necessary to modify a particular chip, access to the transistors and circuitry near the circuit side is obtained only from the back side of the chip. This is challenging since the transistors are in a very thin layer (about 10 micrometers) of silicon buried under the bulk silicon (greater than 500 micrometers). Thus, the circuit side of the flip chip die is not visible or accessible for viewing using optical or scanning electron microscopy.
Although the circuit of the integrated circuit (IC) is buried under the bulk silicon, infrared (IR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of IR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using IR microscopy. On a die that is 725 microns thick, this means removing at least 625 microns of silicon before IR microscopy can be used. Thinning the die for failure analysis of a flip chip bonded IC is usually accomplished in two or three steps. First, the die is thinned across the whole die surface. This is also referred to as global thinning. Global thinning is done to allow viewing of the active circuit from the back side of the die using IR microscopy. Mechanical polishing is one method for global thinning.
Once an area is identified as an area of interest and it is determined that access is needed to a particular area of the circuit, local thinning techniques can be used to thin an area smaller than the die size. Laser microchemical etching of silicon is one method of local thinning.
Sometimes it is necessary for failure analysis, or for design debug, after global and/or local thinning, to make electrical contact and probe certain nodes in the circuit. This testing can be performed via the thinned back side or via pads on the circuit side of the chip. When testing via pads on the circuit side of the chip, the chip is typically placed in a test fixture having a circuit connector arranged to connect to these circuit-side pads. The chip is activated through the test fixture, and signals at the nodes are analyzed. For certain applications, it has been discovered in connection with the present invention that the above-described thinning to remove substrate material results in the circuitry over-heating. When there is insufficient substrate material for drawing heat away from the internal circuitry, for example, when the circuitry is running at high speeds, the internal circuitry overheats and becomes inoperative. Consequently, the analysis/debug efforts are destroyed.
Accordingly, there is a need for a testing approach that overcomes the above-mentioned shortcomings.
SUMMARY OF THE INVENTION
According to one aspect of the disclosure, the present invention provides an approach for testing a flip chip semiconductor device after the back side of the chip has been thinned to expose a selected region in the substrate. Thinning removes substrate material useful for drawing heat away from the internal circuitry when the circuitry is running at high speeds. To compensate for this material loss, a plurality of thermally conduc
Birdsley Jeffrey D.
Bruce Michael R.
Davis Brennan V.
Goruganthu Rama R.
Ring Rosalinda M.
Advanced Micro Devices , Inc.
Christianson Keith
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