Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2002-06-24
2003-10-07
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S691000, C438S014000
Reexamination Certificate
active
06630685
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to testing of semiconductor dies disposed on a semiconductor substrate.
BACKGROUND OF THE INVENTION
After a semiconductor wafer has been fabricated, a number of the dies on the wafer are inoperable. Manufacturers of semiconductor devices typically test the individual dies for functionality prior to singulation into individual dies, to evaluate various electrical parameters of the integrated circuit components contained on each die, and verify that certain standards are met. Integrated circuits (IC) devices typically undergo three separate test cycles: (1) in-process testing and monitoring of sheet resistivities, junction depths, and device parameters such as current gain and voltage breakdown; (2) wafer-probe testing of electrical parameters prior to die separation; and (3) final testing of reliability and performance after die packaging is completed. Testing of ICs is expensive and time consuming, and it is desirable to keep testing costs low since these add directly to the cost of producing the parts.
Semiconductor wafers are typically subjected to test probing tested prior to singulation into individuals dies using a wafer-level test system. As illustrated in
FIG. 1
, a typical test system
10
includes a wafer handler
12
for handling and positioning the wafers
14
, a test circuit
16
for generating test signals, a probe card (probe head)
18
, and a probe interface board
20
for routing signals from the test circuit electronics to the probe card
18
. The wafer probe card
18
typically includes multiple probe elements
22
, typically in the form of probe pins or needles, for making temporary electrical connections with contacts on the dies disposed on the wafer
14
, the contacts typically in the form of bond pads, fuse pads or test pads arranged in a dense area array. The wafer handler
12
typically includes a wafer chuck
24
configured to move in X and Y directions (i.e., horizontally backward-forward and side-to-side) to align the wafer
14
with the probe card
18
, and in the Z direction (vertically up-down) to move the wafer into contact with the probe pins
22
. Exemplary prior art test systems are described, for example, in U.S. Pat. Nos. 6,300,786 (Doherty, et al.) and U.S. Pat. No. 6,246,245 (Akram et al.), both assigned to Micron Technology, Inc.), the disclosures of which are incorporated herein.
An example of a prior art semiconductor wafer
14
is illustrated in
FIGS. 2-3
. The wafer
14
includes multiple semiconductor chips or dies
26
fabricated using processes that are well known in the art. The dies
26
are typically singulated by use of a wafer saw, which grinds the wafer
14
along wafer scribe lines
28
, usually referred to “streets” or “avenues”, that separate the dies
26
from each other. As shown in
FIG. 3
, each die
26
includes multiple die pads
30
. The die pads
30
are in electrical communication with integrated circuits contained on the die
26
. For illustrative purposes, each die
26
includes eight die pads
30
, which is merely exemplary. The die pads
30
are illustrated as bond pads, but can also be dedicated test pads or fuse pads, disposed on the dies
26
or on other portions of the wafer
14
.
Conventionally, each die on a wafer is tested by placing the probe elements
22
of a probe card connected to a test system on the pads
30
of the die. The test system supplies the proper power levels and signals to the pads on the die.
An example of a prior art probe card
18
is illustrated in
FIG. 4
, and typically comprises an insulating substrate
21
, such as a glass filled resin, that includes electric traces (not shown) in electrical communication with the contacts or probe pins
22
. The probe pins
22
on the probe card
1
8
are arranged in patterns corresponding to the patterns of the die pads
30
. The probe pins
22
can be configured to make electrical connections with the die pads
30
on a specific die
26
or, as in the illustration in
FIG. 4
, with a group of dies (i.e., four dies) on the wafer. The probe pins
22
on the probe card
18
are arranged in groups
32
a-d
and configured on the substrate to correspond to the pattern of the die pads
30
on the die
26
to be contacted. Each group
32
a-d
of probe pins
22
represents a single test site. Typically, two or more test sites are included on the probe card
18
to accommodate testing of multiple dies at the same time. The probe card
18
can be formed with any desired number of test sites. The probe card
18
can also be configured to test a complete semiconductor wafer
14
, or a portion of the dies
26
in a partial wafer. In the illustrated example in
FIG. 4
, the probe card
18
includes four test sites such that four dies
26
on the wafer
14
can be tested simultaneously. During a test procedure using a probe card, stepping techniques can be used to step the wafer
14
or the probe card
18
, and test a number of dies
26
within a section on the wafer until all the dies
26
on the wafer have been tested. In those cases where dies
26
are positioned along the peripheral edge of a round wafer
14
(not shown), some of the probe pin groups
32
a-d
may not have an associated die under test, and the software that controls the stepping process is typically programmed to register valid test sites.
Manufacturers of semiconductor memory devices typically perform several operations on each device to examine various electrical parameters of the device and verify that certain minimum standards are met. A full range of functionality and timing characteristics of the memory devices are tested in order to determine if there is a defect in the array of cells that may fail over time. The test system
16
can transmit specific combinations of voltages and currents and/or signals to the probe interface board
20
and through the probe pins
22
of the probe card
18
to dies
26
under probe on the semiconductor wafer.
Bum-in stressing of dies is typically performed to accelerate failure using elevated voltage and temperature levels to stress, and determine operable voltages, currents, and temperatures. The test system can also run diagnostic tests on the memory device(s), which includes furnishing a sequence of commands (e.g., address, data and control signals) to the memory device for storing first data in memory cells of the memory device. The memory device can perform operations in response to the commands, and the operations synchronized to a clock signal. After the sequence, second data can be read from the memory cells and the first and second data can be compared to detect memory speed, timing, failures, and so forth. The integrated circuits that do not meet specification can be marked or mapped in software. Following testing, defective circuits can be repaired by actuating fuses (or anti-fuses) to inactivate the defective circuitry and substitute redundant circuitry.
In addition to the use of an external test system, memory testing can also be performed by means of a built-in self-test (BIST) circuit, which incorporates test circuitry and test data into the die
26
itself. In a BIST operation, the die is run in a way similar to how it is ultimately meant to be run. Activating BIST circuitry requires a Vcc power source, GND ground potential, and can also require signals from a test system. On a wafer level, the BIST circuitry can be disposed in the scribe lines (“streets”)
28
between dies
26
or in the unused edge portions along the periphery
34
of the wafer
14
, or can be included within the dies
26
themselves.
Because each memory cell or bit of the memory device must be tested, the time and equipment necessary for testing memory devices represents a significant portion of the overall manufacturing cost of such devices. The more chips that can be tested simultaneously, the greater the savings in testing time and manufacturing cost per chip. Still more time could be saved if different testing protocols could be performed on a plurality of memory devices simultaneously.
SUMMARY OF THE INVENTI
Clark Sheila V.
Whyte Hirschboeck Dudek SC
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