Priority request and bypass bus

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

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Details

710 36, 710 40, 710 52, G06F 1318

Patent

active

059832991

ABSTRACT:
To reduce latency for priority requests in a bus system, non-priority requests to a bus device are separated from priority requests so that the priority requests can be processed before the non-priority requests. Priority requests are transferred over a priority request bus. Standard non-priority requests are sent over a shared bus coupled to several bus devices. One of the bus devices contains a request buffer to receive non-priority requests from the shared bus and a priority buffer to receive priority requests from the priority request bus. Requests in the priority buffer are processed before requests in the request buffer. In one embodiment, a multiplexer having input ports coupled to the request buffer and the priority buffer is configured so that the multiplexer outputs priority requests if there are priority requests in the priority buffer. Some embodiments of the bus communication system incorporate a priority bypass bus which transfers priority data directly to a peripheral device coupled to the first bus device.

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