Printed circuit substrate with solder formed on pad-on-via and p

Details Printed circuit substrate with solder formed on pad-on-via and p Printed circuit substrate with solder formed on pad-on-via and p

1996-11-12

2000-02-01

Kincaid, Kristine

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

174263, 22818022, 361777, 361774, H01R 909

Patent

active

06020561&

ABSTRACT:
A printed circuit substrate having solder bumps formed on pad-on-via contacts and pad-off-via contacts. The printed circuit substrate has at least one pad-on-via contact and at least one pad-off-via contact. A first solder bump is on the pad-on-via contact and a second solder bump is on the pad-off-via contact. The first and second solder bumps are substantially the same height as measured above a horizontal plane that is substantially co-planar to the pad-off-via contact.

REFERENCES:
patent: 3458925 (1969-08-01), Napier et al.
patent: 4764804 (1988-08-01), Sahara et al.
patent: 5214308 (1993-05-01), Nishiguchi et al.
patent: 5255839 (1993-10-01), da Costa Alves et al.
patent: 5261593 (1993-11-01), Casson et al.
patent: 5400950 (1995-03-01), Myers et al.
patent: 5489750 (1996-02-01), Sakemi et al.
patent: 5493075 (1996-02-01), Chong et al.
patent: 5521435 (1996-05-01), Mizukoshi
patent: 5591941 (1997-01-01), Acocella et al.

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