Prevention of post CMP defects in CU/FSG process

Details Prevention of post CMP defects in CU/FSG process Prevention of post CMP defects in CU/FSG process

2006-08-15

2006-08-15

Abraham, Fetsum (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S700000

Reexamination Certificate

active

07091600

ABSTRACT:
A common problem associated with damascene structures made of copper inlaid in FSG (fluorinated silicate glass) is the formation of defects near the top surface of the structure. The present invention avoids this problem by laying down a layer of USG (undoped silicate glass) over the surface of the FSG layer prior to patterning and etching the latter to form the via hole and (for a dual damascene structure) the trench. After over-filling with copper, the structure is planarized using CMP. The USG layer acts both to prevent any fluorine from the FSG layer from reaching the copper and as an end-point detector during CMP. In this way defects that result from copper-fluorine interaction do not form and precise planarization is achieved.

REFERENCES:
patent: 6008120 (1999-12-01), Lee
patent: 6103601 (2000-08-01), Lee et al.
patent: 6121164 (2000-09-01), Yieh et al.
patent: 6130157 (2000-10-01), Liu et al.
patent: 6136680 (2000-10-01), Lai et al.
patent: 6150272 (2000-11-01), Liu et al.
patent: 6319814 (2001-11-01), Tsai et al.

Affiliated with

Also associated with

Rating

Prevention of post CMP defects in CU/FSG process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Prevention of post CMP defects in CU/FSG process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Prevention of post CMP defects in CU/FSG process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3714989