Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Metastable state prevention
Reexamination Certificate
2005-06-14
2005-06-14
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Metastable state prevention
C327S155000, C375S357000
Reexamination Certificate
active
06906555
ABSTRACT:
Methods and apparatus implementing techniques for prevention of metastability in a bistable circuit. The techniques include detecting a change in a data signal, sampling the detected change in reference to a sampling window of a clock signal input of a bistable circuit to determine if the detected change occurs within the sampling window, and selecting a stable data input to present to an input of the bistable circuit based on whether the detected change occurs within the sampling window. The sampling window represents a time period during which a change in the data signal can cause metastability in a bistable circuit.
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Chang Daniel D.
Fish & Richardson P.C.
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