Prevention of inter-channel current leakage in semiconductors

Details Prevention of inter-channel current leakage in semiconductors Prevention of inter-channel current leakage in semiconductors

1999-05-28

2002-10-15

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S386000, C438S637000, C438S695000, C257S303000, C257S306000

Reexamination Certificate

active

06465345

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor manufacturing and more a method for preventing inter-channel current leakage.
BACKGROUND ART
While manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the “damascene” technique, starts with the placement of a patterned etch stop layer, which is typically a silicon nitride “nitride” layer, over the semiconductor devices followed by a first channel dielectric layer, which is typically a silicon dioxide, “oxide” layer. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic dielectric etch is then used to etch out the channel dielectric layer to form the first channel openings in contrast with the semiconductor devices. The damascene step photoresist is stripped and an optional thin adhesion layer is deposited to coat the walls of the first channel openings to ensure good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices. A barrier layer is then deposited on the adhesion layer to improve the formation of subsequently deposited conductive material and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as “barrier layer herein). It should be noted that some barrier materials also have good adhesion which is why the adhesion layer is optional. A “seed” layer is then deposited to act as a seed for additional conductive material to be deposited. A first conductive material is then deposited and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel dielectric layer and damascenes the first conductive material in the first channel openings to form the first channels.
Often, there are atoms of the barrier, seed, and conductive material left on the first channel dielectric layer after the chemical-mechanical polishing. These atoms present a problem because they offer a current path to allow leakage of electrical current between the various first channels. This adversely affects the performance of the entire integrated circuit.
For multiple layers of channels, another metalization process, which is called the “dual damascene” technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene process starts with the deposition of a thin patterned etch stop layer, which is generally a nitride, over the first channels and the first channel dielectric layer.
Subsequently, a separating oxide layer is deposited on the etch stop. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels. A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel dielectric layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel dielectric layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin etch stop layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. An adhesion layer is then deposited to coat the via openings and the second channel openings. Next, a barrier layer is deposited on the adhesion layer. This is followed by a deposition of the second conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
For two layers of channels, various types of capping layers are deposited with patterning for bonding pads which would be used to connect to external electrical connections. Where there are additional layers of metalization, the dual damascene process would be repeated to produce the desired number of channels.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One of the problems of using copper is that it diffuses rapidly through various materials. This means that the copper atoms which may be left after chemical-mechanical polishing will diffuse and create leakage paths for current between the various channels in each level.
A solution, which would simply eliminate contamination of dielectric layers after chemical-mechanical polishing, has been long sought. As the semiconductor industry is moving from aluminum to copper and other types of high conductivity materials in order to obtain higher semiconductor circuit speeds, it is becoming more pressing that a solution be found.
DISCLOSURE OF THE INVENTION
The present invention provides a method for removing the atomic residue of conductive materials left on the channel dielectric layers of semiconductors after planarization. After planarization and removal of such atomic residue, an etch stop layer is deposited on the channel dielectric which eliminates the leakage of current between the conductive channels.
The present invention further provides a method for removing the atomic residue of copper from the silicon dioxide dielectric layer of a semiconductor after chemical-mechanical polishing. After chemical-mechanical polishing and removal of the atomic residue of copper, the silicon nitride layer is deposited onto the silicon dioxide to eliminate leakage current through the silicon nitride/silicon oxide interface.
The present invention further provides a method for using a chemical-vapor deposition system for plasma etching by changing the gas mixture in the system's vacuum chamber.
The present invention further provides a method for using a silicon nitride chemicalvapor deposition system for plasma etching a silicon dioxide layer.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.


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Wolf and Tauber; Silicon Processing for the VLSI Era vol. 1: Process Technology pp. 161, 191-195; Lattice Press, NY; ® 1986.*
Wolf, Stanley and Tauber Richard; Silicon Processing for the VLSI Era, vol. 1; copyright 1986 Lattice Press, Sunset Beach, California; pp. 171-174 and 542-551.

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