Prevention of erroneous operation in equalizing operation in sem

Details Prevention of erroneous operation in equalizing operation in sem Prevention of erroneous operation in equalizing operation in sem

1996-09-18

1998-05-05

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, 365205, G11C 700

Patent

active

057485402

ABSTRACT:
In a semiconductor memory device, a data is written in a memory cell through a pair of digit lines during a write operation time interval. An equalizing operation is performed to the pair of digit lines in response to an equalizing control signal during the write operation time interval to recover potentials of the digit lines. In order to suppress output change of a sense amplifier circuit on the equalizing operation, a load of the sense amplifier circuit is changed in response to the equalizing control signal by a flip-flop circuit such that the load becomes heavier than that before the equalizing operation. The flip-flop circuit is composed of a flip-flop section, and first and second transfer gates connected between the outputs of the sense amplifier circuit and the inputs of the flip-flop section. The first and second transfer gates are set to the conductive state in response to the equalizing control signal. The flip-flop section is composed of two inverter circuits which are connected such that an input of one of the two inverter circuits is connected to an output of the other and each inverter circuit is composed of a load and a transistor connected in series.

REFERENCES:
patent: 4943944 (1990-07-01), Sakui et al.
patent: 5068831 (1991-11-01), Hoshi et al.
Yasuhiko Maki, et al., "Session 8: Static RAMs, TPM 8.6: A 6.5ns 1Mb BiCMOS EL SRAM", IEEE International Solid-State Circuits Conference, Feb. 15, 1990, pp. 136-137.

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