Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-01
2002-04-30
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S558000, C438S559000, C438S563000, C438S664000, C438S682000
Reexamination Certificate
active
06380040
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device comprising refractory metal silicide contacts to source/drain and silicon gate regions. The present invention has particular applicability in manufacturing reliable high density semiconductor devices with submicron design features, shallow junction depths and cobalt silicide contacts to source/drain regions.
BACKGROUND ART
Current demands for high density and performance associated with ultra large scale integration require design rules of about 0.18 microns and under, increased transistor and circuit speeds and improved reliability. As device scaling plunges into the deep sub-micron ranges, it becomes increasingly difficult to maintain performance and reliability.
In the manufacture of conventional complementary metal oxide semiconductor (CMOS) devices, referring to
FIG. 1A
, isolation regions
110
, called field oxide regions, are formed in a semiconductor substrate
100
of silicon dioxide by local oxidation of silicon (LOCOS) or by shallow trench isolation (STI). A conductive gate
130
, such as polysilicon, is also formed on substrate
100
, with a gate oxide layer
120
in between. Dielectric spacers
140
are formed on sidewalls of the gate
130
, and source/drain regions
150
are formed on either side of gate
130
by implantation of impurities.
As gate lengths are reduced to below 0.5 &mgr;, refractory metal silicide layers, such as titanium silicide, are typically formed over source/drain regions
150
and gate
130
to reduce the sheet resistivity of these components, thereby improving device performance. Referring to
FIG. 1B
, a titanium layer
160
is deposited, as by sputtering, over the entire substrate
100
as well as field oxide
110
, gate
130
and spacers
140
. A low temperature rapid thermal anneal (RTA) reaction creates a first-phase titanium silicide (C
49
) on the exposed silicon of gate
130
and source/drain regions
150
. The unreacted titanium over field oxide
110
and spacers
140
is then removed, and a high temperature RTA reaction changes the first-phase titanium silicide into a low-resistivity second-phase titanium silicide
170
(C
54
), as shown in FIG.
1
C. Since the titanium silicide does not form on field oxide
110
or spacers
140
, it is self-aligned to the gate
130
and source/drain regions
150
. Hence, the titanium silicide formed in this process is known as “titanium salicide” (self-aligned silicide).
Titanium salicide is effective in decreasing sheet resistivity if the gate length is greater than about 0.25 &mgr;. At a gate length of about 0.25 &mgr; the titanium silicide sheet resistance rises dramatically due to narrow-line effects; that is, the low-resistivity silicide C
54
does not completely form because first-phase C
49
grains are very large (about 0.5 &mgr;), and hence it is not possible to fit enough grains on the gate to nucleate and grow a sufficient amount of C
54
.
To maintain low sheet resistance as gate lengths are decreased in scale below about 0.25 &mgr;, cobalt is typically used instead of titanium in silicide formation. Cobalt silicide does not display the undesirable narrow-line effects of titanium silicide because the conversion from its first-phase cobalt silicide to its low-resistivity second-phase cobalt silicide is a diffusion reaction, rather than the nucleation and growth reaction of titanium silicide, and therefore the relationship of grain size to gate size is not a limiting factor.
However, the cobalt salicide process has a drawback in that cobalt silicide is more likely than titanium silicide to cause source and drain junction leakage, which can result in unacceptably high power dissipation as well as functional failure. This problem becomes especially critical as gate lengths are scaled below 0.25 &mgr;, and source and drain junctions are typically made shallower to prevent transistor short-channel effects. Since shallow junctions are more susceptible to junction leakage than deep junctions, cobalt silicide related junction leakage effectively limits CMOS device scaling.
A cause of this junction leakage, referring to
FIG. 2
, is the unevenness of the interface between the cobalt silicide
210
and the silicon source/drain regions
220
, which results in an insufficient distance between portions of the bottom of the cobalt silicide
210
and source/drain junctions
220
a
. When a junction
220
a
is biased, a depletion region (i.e., an area depleted of free carriers) is formed which extends on either side of the junction
220
a
. Since the distance the depletion region spreads from the junction
220
a
is inversely proportional to the doping of the region, and source/drain region
220
is more heavily doped than substrate
200
, the depletion region spreads mainly into substrate
200
. Nevertheless, if cobalt silicide
210
extends into the depletion spread, leakage can occur as carriers are swept across this highly charged region.
Junction leakage also occurs due to consumption of silicon of substrate
200
during silicide formation. For example, when cobalt silicide is formed to a given thickness, a thickness of substrate silicon slightly greater than the thickness of the silicide is consumed. As junctions become shallower with device scaling, consumption of substrate silicon during silicidation results in an insufficient distance between portions of the bottom of the cobalt silicide
210
and source/drain junctions
220
a
and, hence, junction leakage. Junction integrity can be maintained by providing a large enough distance between junction
220
a
and the interface of silicide
210
and source/drain region
220
; i.e., by reducing the thickness of cobalt silicide
210
. However, reducing its thickness increases the sheet resistivity of cobalt silicide
210
, thus reducing its effectiveness.
Copending U.S. patent application Ser. No. 09/187,427 and U.S. Pat. No. 6,096,399 disclose methodologies for forming junctions self-aligned to the bottom of the cobalt silicide, thus avoiding junction leakage by addressing the problem of insufficient distance between portions of the bottom of the silicide and the source/drain junctions. According to these methodologies, a doped film is deposited on top of the cobalt or cobalt silicide, from which impurities are diffused through the cobalt silicide to form source/drain regions having a junction depth which is substantially evenly spaced from the metal silicide/silicon interface.
Copending U.S. patent application Ser. No. 09/318,824 addresses the problem of substrate silicon consumption during silicidation, facilitating the formation of shallower source/drain junctions demanded as devices are further scaled. According to this methodology, a doped amorphous silicon film is deposited on top of the cobalt. The amorphous silicon film is consumed during silicidation, thereby decreasing the amount of substrate silicon consumed, and the dopant is diffused through the cobalt silicide to form source/drain regions having ultra-shallow junctions substantially evenly spaced from the metal silicide/silicon interface.
Disadvantageously, when implementing the methodologies of U.S. Pat. No. 6,096,599 and copending applications Ser. Nos. 09/187,427 and 09/318,824, the impurities may diffuse, upon heating, out of the doped film and into the environment rather than into the substrate. This may occur whether the diffusion step is carried out at the low temperature RTA step, the high temperature RTA step, or at a separate heating step. As a result of unwanted out-diffusion, the amount of impurities available to dope the substrate may be insufficient to properly form the source/drain regions.
There exists a need for a method of manufacturing a semiconductor device by diffusing impurities from a doped layer into the substrate during or after silicidation to form source/drain regions, without a loss of dopant due to out-diffusion of impurities to the environment.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor de
Besser Paul R.
Kepler Nick
Wang Larry
Wieczorek Karsten
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