Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2004-06-28
2008-12-02
Smith, Zandra (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S639000, C438S640000, C438S643000
Reexamination Certificate
active
07459384
ABSTRACT:
Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.
REFERENCES:
patent: 6228731 (2001-05-01), Liaw et al.
patent: 6369430 (2002-04-01), Adetutu et al.
patent: 6500771 (2002-12-01), Vassiliev et al.
patent: 6613657 (2003-09-01), Ngo et al.
patent: 6649500 (2003-11-01), Koga
patent: 6774441 (2004-08-01), Maki et al.
patent: 2004/0061169 (2004-04-01), Leam et al.
patent: 2005/0051833 (2005-03-01), Wang et al.
Agnello Paul D.
Malik Rajeev
Muller K. Paul
Duong Khanh B
Hoffman Warnick LLC
International Business Machines - Corporation
Smith Zandra
Urich Lisa J.
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