Preparation of strained Si/SiGe on insulator by hydrogen...

Details Preparation of strained Si/SiGe on insulator by hydrogen... Preparation of strained Si/SiGe on insulator by hydrogen...

2000-09-29

2003-02-25

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

C438S458000, C438S507000, C438S479000

Reexamination Certificate

active

06524935

ABSTRACT:

FIELD OF INVENTION
This invention relates to Si/SiGe layers on an insulator (SGOI) and more particularly to strained Si/SiGe layers on an insulator structure which is useful for fabricating high speed devices such as complementary metal-oxide-semiconductor (CMOS) transistors, modulation-doped field-effect-transistors (MODFETs), high electron mobility transistors (HEMTs) and bipolar transistors.
BACKGROUND OF THE INVENTION
Electron mobility in strained Si/SiGe channels is significantly higher than that in bulk Si. For example, measured values of electron mobility in strained Si at room temperature are about 3000 cm
2
/Vs as opposed to 400 cm
2
/Vs in bulk Si. Similarly, hole mobility in strained SiGe with high Ge concentration (60%~80%) reaches up to 800 cm
2
/Vs, the value of which is about 5 times the hole mobility in bulk Si of 150 cm
2
/Vs. The use of strained crystalline materials in state-of-the-art Si devices is expected to result in much higher performances, higher operating speeds in particular. Strained Si/SiGe is of particular significance when conventional Si devices continue to scale down to 0.1 &mgr;m regime and start to approach the fundamental limits of unstrained materials.
However, the underlying conducting substrate for MODFETs and bipolar transistors or the interaction of the underlying substrate with the active device regions in CMOS are undesirable features which limit the full performance of high speed devices. To resolve the problem, in Si technology, an insulating layer is usually used to isolate the active device region from the substrate before creating Silicon-On-Insulator (SOI) materials to replace bulk Si material for device fabrication. Available technology to achieve SOI wafers includes Separation by Implanted Oxygen (SIMOX), bonding and etchback Silicon-On-Insulator (BESOI), separation by implanted hydrogen also known as the Smart-Cut® process which is described in U.S. Pat. No. 5,374,564 by M. Bruel which issued Dec. 20, 1994, or the combination of the last two processes for making ultra-thin SOI, U.S. Pat. No. 5,882,987 by K. V. Srikrishnan which issued Mar. 16, 1999.
When Si is substituted by strained Si/SiGe layers for high speed applications, there is a need for techniques capable of providing SiGe on insulator substrates or wafers for the fabrication of strained Si/SiGe on insulator materials. In U.S. Pat. No. 5,906,951 by Chu et al. which issued May 25, 1999, a method of utilizing wafer bonding and backside etching in KOH with a p
++
-doped SiGe etch-stop to form a layer of strained Si/SiGe on a SOI substrate was described. However, the etch-stop layer is heavily doped by boron in the range from 5×10
19
to 5×10
2
atoms/cm
3
and therefore there are chances of the boron auto-doping the strained Si/SiGe layers during thermal treatment. Furthermore, the strained Si/SiGe layer may also be subjected to unwanted KOH etching if etching could not stop uniformly at the p
++
SiGe etchstop layer due to variation of dopants in the p
++
layer.
Another available technique for making SiGe-On-Insulator is via SIMOX as reported in a publication by T. Mizuno et al. entitled “High Performance Strained-Si p-MOSFETs on SiGe-on-Insulator Substrates Fabricated by SIMOX Technology,” IEDM Technical Digest, 99-934, 1999. However, this method has limited applications because the oxygen implantation induces further damage in the relaxed SiGe layer in addition to the existing defects caused by lattice mismatch, which may consequently degrade the quality of the grown strained Si/SiGe. And, the high temperature anneal (>1100° C.) needed to form oxide after the oxygen implantation is detrimental to the strained Si/SiGe layers since Ge tends to diffuse and agglomerate at temperatures above 600° C., this effect becomes more significant when the Ge content is higher than 10%. Furthermore, in this method, the insulator is limited to SiO
2
which has lower thermal conductivity compared to other insulators such as Al
2
O
3
.
Therefore, there is a need for a method which is capable of fabricating strained Si/SiGe-On-Insulator wafers or substrates with high quality, i.e., low defect density, and which provides the flexibility of integrating different kinds of materials of desired properties to the substrate, and which has a better controllability for the manufacturing purpose.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for forming a substrate suitable for growing high quality strained Si/SiGe layers on an insulator (SGOI) is described. This approach comprises the steps of selecting a first semiconductor substrate, forming a first expitaxial graded layer of Si
1−x
Ge
x
, over the first semiconductor substrate, forming a second relaxed Si
1−y
Ge
y
, layer over the first graded layer, introducing hydrogen into the relaxed Si
1−y
Ge
y
layer creating a hydrogen-rich defective layer comprising high density point defects and micro-cracks, the defective layer being within the relaxed Si
1−y
Ge
y
layer, smoothing the surface of the relaxed SiGe epitaxial layer, selecting a second substrate having a layer of insulator such as SiO
2
, Si
3
N
4
, Al
2
O
3
, or other acceptable or qualified low-k insulating materials, etc, on the second substrate, and having a planarized major surface on the second substrate, bonding the major surface of the first substrate to the major surface of the second substrate including the step of annealing to form a joined substrate pair with an insulator layer therein between, applying thermal treatments to the substrate pair to induce separation at the hydrogen-rich defective layer, the separation occurring to form a first structure containing the first substrate and a second structure containing the second substrate with a relaxed Si
1−y
Ge
y
layer on insulator. The invention further includes smoothing the upper surface of the relaxed Si
1−y
Ge
y
layer on said second substrate whereby the second structure is suitable for subsequent epitaxial growth of strained Si/SiGe layers for MOSFET, MODFET, HEMT or bipolar transistor device applications.


REFERENCES:
patent: 6107653 (2000-08-01), Fitzgerald
patent: 6313016 (2001-11-01), Kibbel et al.
patent: 6323108 (2001-11-01), Kub et al.

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