Prefetching variable length data

Details Prefetching variable length data Prefetching variable length data

1995-05-22

1998-06-02

Harvey, Jack B.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711171, 395584, G06F 1300

Patent

active

057614644

ABSTRACT:
An interface unit connected between a first bus and a second bus, the first bus having connected thereto a memory system and the second bus having connected thereto a plurality of devices which perform read operations directed at the memory system, the interface unit including a buffer memory having an input that is electrically coupled to the first bus for receiving data that is sent from the memory system over the first bus and an output that is electrically coupled to the second bus for delivering data to the second bus for transfer to a requesting device, the requesting device being one of the plurality of devices; a plurality of prefetch size registers equal in number to the plurality of devices, wherein each of the plurality of prefetch size registers stores a number for a different corresponding one of the plurality of devices, wherein the number stored in each of the plurality of prefetch size registers specifies an amount of data that is prefetched from memory in response to a data read request from the corresponding device; and a control unit which in response to a data read request from any one of the plurality of devices prefetches into the buffer a predetermined amount of data from the system memory, the predetermined amount being determined by the number stored in prefetch size register corresponding to the requesting device.

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