Predicting output of a reuse region using prior execution...

Details Predicting output of a reuse region using prior execution... Predicting output of a reuse region using prior execution...

2000-06-29

2004-12-28

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C712S220000

Reexamination Certificate

active

06836841

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to microprocessors, and more specifically to microprocessors capable of speculatively reusing regions of software code.
BACKGROUND OF THE INVENTION
Modern software programs include many instructions that are executed multiple times each time the program is executed. Typically, large programs have logical “regions” of instructions, each of which may be executed many times. When a region is one that is executed more than once, and the results produced by the region are the same for more than one execution, the region is a candidate for “reuse.” The term “reuse” refers to the reusing of results from a previous execution of the region.
For example, a reuse region could be a region of software instructions that, when executed, read a first set of registers and modify a second set of registers. The data values in the first set of registers are the “inputs” to the reuse region, and the data values deposited into the second set of registers are the “results” of the reuse region. A buffer holding inputs and results can be maintained for the region. Each entry in the buffer is termed an “instance.” When the region is encountered during execution of the program, the buffer is consulted and if an instance with matching input values is found, the results can be used without having to execute the software instructions in the reuse region. When reusing the results is faster than executing the software instructions in the region, performance improves.
However, in order to achieve performance improvement, a large number of instances must be maintained for each reuse region, thereby increasing the cost involved in reusing regions of software instructions. Similarly, when execution of a reuse region creates a large number of results, reuse is costly and inefficient as the likelihood of reusing each of the multiple results decreases.
Another problem with reuse arises when the reuse region contains a memory load instruction that accesses a memory location modified by a memory update instruction outside the region. For such regions (called “aliased” regions), even when a matching instance exists in the buffer, the reuse instance may not be usable because the aliased memory load may read a different value that causes the correct results to differ from the results in the instance. Furthermore, current microprocessors lack any reuse capability when no matching instance is found in the buffer.
Therefore, it would be advantageous to provide an alternate method and apparatus for reusing regions of software code.


REFERENCES:
patent: 5742805 (1998-04-01), Kulkarni et al.
Huang, Jian et al. “Exploiting Basic Block Value Locality with Block Reuse”, Jan. 13, 2003, Fifth International Symposium OnHigh-Performance Computer Architecture, 1999. Proceedings. pp. 106-114.*
Gonzalez, Antonio et al. “Trace-Level Reuse”, Sep. 24, 1999, 1999 International Conference on Parallel Processing, 1999. Proceedings. pp. 30-37.*
Connors, D., et al., “Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results,” 32th International Symposium on Microarchitecture (Micro32), Nov.-Dec. 1999.
Marcuello, P., et al., “Value Prediction for Speculative Multithreaded Architectures,” 32th International Symposium on Microarchitecture (Micro32), Nov.-Dec. 1999.

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