Electrical computers and digital processing systems: memory – Address formation – Hashing
Reexamination Certificate
2007-05-15
2007-05-15
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Hashing
Reexamination Certificate
active
10298606
ABSTRACT:
A system precomputes data for possible use by a processor. The system receives data units, and determines the types of the data units. The system then identifies one or more bit masks based on the types of the data units, where the one or more bit masks include bits corresponding to at least some portions of the data units. The system uses the one or more bit masks to select one or more portions of the data units and perform one or more functions using the one or more portions of the data units to generate function results. The system stores the function results in a first memory for subsequent selective use by the processor, and stores the data units in a second memory for subsequent retrieval by the processor.
REFERENCES:
patent: 6141421 (2000-10-01), Takaragi et al.
patent: 6167480 (2000-12-01), Williams et al.
patent: 6173384 (2001-01-01), Weaver
patent: 6181698 (2001-01-01), Hariguchi
patent: 6223172 (2001-04-01), Hunter et al.
patent: 6301629 (2001-10-01), Sastri et al.
patent: 6487626 (2002-11-01), Gray et al.
patent: 6570884 (2003-05-01), Connery et al.
patent: 6578131 (2003-06-01), Larson et al.
patent: 6675163 (2004-01-01), Bass et al.
patent: 6697276 (2004-02-01), Pereira et al.
patent: 6907466 (2005-06-01), Alexander, Jr. et al.
patent: 6915344 (2005-07-01), Rowe et al.
patent: 2002/0097724 (2002-07-01), Halme et al.
patent: 2002/0161911 (2002-10-01), Pinckney et al.
patent: 2003/0177435 (2003-09-01), Budd et al.
patent: 2003/0189932 (2003-10-01), Ishikawa et al.
patent: 2004/0034823 (2004-02-01), Watkins et al.
“A Packet Classification and Filter Management System,” V. Srinivasan, Proceedings of IEEE Infocom, 2001, 2001, vol. 3, pp. 1464-1473.
“Efficient Simulation Compute Power with Enhanced Testcase Generation Scheme,” R. Jesssani, S. Malllick, R. Patel, and L. Powell, IBM Technical Disclosure bulletin, 1996, vol. 39, No. 05, pp. 163-166.
A. Rijsinghani: “Computation of the Internet Checksum via Incremental Update,” Request for Comments: 1624, May 1994, pp. 1-6.
Greene Spencer
Möller Olaf
Washburn James
Harrity & Snyder LLP
Juniper Networks, Inc.
Kim Matthew
Krofcheck Michael
LandOfFree
Precompute logic for software packet processing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Precompute logic for software packet processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Precompute logic for software packet processing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3751756