Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Patent
1996-12-03
1999-06-15
Dinh, Son T.
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
365206, 365207, 327 51, 327 52, 327 57, G11C 700
Patent
active
059128534
ABSTRACT:
An amplifier 300 includes a differential pair of transistors 307a, 307b. A third transistor 306 controls current through transistors 307a, 307b of the differential pair in response to a stepped control signal.
REFERENCES:
patent: 5420823 (1995-05-01), Yonaga et al.
patent: 5477498 (1995-12-01), Ooishi
patent: 5526314 (1996-06-01), Kumar
"A 64-K Dynamic RAM Needs Only One 5-Volt Supply To Outstrip 16K Parts" G. R. Mohen Rao & John Hewkins, Electronics, Sep., 28, 1978 pp. 109-116.
"A 1Mb CMOS DRAM With Design-For-Test Functions" by Neal, Holland, Inoue Lob, McAdams & Pozeet. ISSC. Conf. 1986, Digest of Tech. Papers pp. 264-265.
"A 4Mb DRAM With Half Internal-Voltage Bitline Precharge," ISSC Conf. 1986, Digest of Tech. Papers, pp. 270-271.
"High Speed Sensing Scheme for CMOS DRAM's," by Dhong, et al., in the IEEE Journal of Solid State Circuit, vol. 23, No. 1, Feb. 1988.
"50-ns 16-Mb DRAM with a 10-ns Data Rate and On-chip ECC," by Kalter, et al. IEEE Journal of Solid State Circuits, vol. 25, No. 5 in Oct., 1990.
"A Variable Precharge Voltage Sensing," by Kiri hata, et al., IEEE Journal of Solid State Circuits, vol. 30, No. 1, in Jan., 1995.
"Cross-Coupled Charge-Transfer Sense Amplifier and Latch Sense Scheme for High-Density FET Memories" by Gray in IBM J. Res. Devel., vol. 24, No. 3, May 1980 pp. 283-290.
"A 5-V-Only 64K Dynamic RAM" by White, et. al. in IEEE Internat'l S. S. Circuits Conf. 1980, Friday, Feb. 15, 1980 pp. 230-231.
"Offset-Triming BitLine Sensing Scheme For Gigabit-Scale DRAM's" by Suh, et al. in The I.E.E.E. Jon S.S. Circuits vol. 31, No. 7, Jul. '96 pp. 1025-1028.
"A Full Bit Prefetch Architecture for Synchronous DRAM's" by Sunaga, et al., IEEE Journ. of SS Cir: vol. 30, No. 9, Sep. '95 pp. 998-1005.
"DRAM Macros for ASIC Chips" by Sunaga, et al. IEEE Jour. of Sol. St. Cir. vol. 30, No. 9, Sep. '95 pp. 1006-1014.
Cirrus Logic Inc.
Dinh Son T.
Murphy James J.
Shaw Steven A.
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