Precharging bitlines for robust reading of latch data

Details Precharging bitlines for robust reading of latch data Precharging bitlines for robust reading of latch data

1993-04-08

1994-11-01

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, 36518901, 36518908, G11C 800, G11C 700

Patent

active

053612299

ABSTRACT:
The bit line for reading data in or writing data out from a CMOS integrated circuit latch is precharged to the trip point voltage of the latch (as determined by the latch's transistor design) shortly before the occurrence of a read operation. The precharging circuitry uses the latch circuit itself to generate the trip point, hence ensuring that the precharging circuit operates properly with regards to the latch characteristics in spite of temperature, voltage and fabrication process variations. The precharging circuitry ensures that during the operation of reading data from the latch, the bit line voltage never causes the latch to completely switch states, since at most the bit line voltage asymptotically approaches the trip point voltage. The precharging circuit is relatively simple, including only two logic gates and three other transistors.

REFERENCES:
patent: 4107556 (1978-08-01), Stewart et al.
patent: 4800300 (1989-01-01), Walters, Jr.
patent: 4820937 (1989-04-01), Hsieh

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