Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-08-09
2001-07-03
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S230030, C365S063000
Reexamination Certificate
active
06256245
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a precharge method thereof capable of reducing the overall chip size by reducing the number of precharge circuits required for precharging a local data input/output line pair.
DESCRIPTION OF THE BACKGROUND ART
The common arrangement of signal lines in semiconductor memory devices having a conventional “stack bank” structure consists of a word line and a local data input/output line pair arranged in the same direction, and a global data input/output line pair arranged perpendicular to the local data input/output line pair. The memory cell array of such a structure includes a plurality of memory cell array banks arranged in the direction of a word line, and a plurality of memory cell array blocks of each memory cell array bank also arranged in the direction of a word line. Each of the memory cell array blocks is partitioned into a predetermined number of separated partial blocks, each of the separated partial blocks being connected to each of the local data input/output line pairs, and each of the separated local data input/output line pairs being in turn connected to each of a plurality of global data input/output line pairs.
Thus, in the conventional stack-bank style semiconductor memory device, not only are the memory cell array blocks separated into a predetermined number of partial blocks, but also the local data input/output line pair of each partial block is likewise separated. Further, precharge circuits for precharging each of the local data input/output line pairs are necessary for each of the predetermined number of separated local data input/output line pairs.
Thus, the conventional stack-bank semiconductor memory device configuration results in a large overall chip size, due to the multiple precharge circuits required.
SUMMARY OF TIE INVENTION
It is an object of the present invention to provide a semiconductor memory device capable of reducing the chip size by reducing the number of precharge circuits required to precharge local data input/output line pairs in a stack bank structure.
It is another object of the present invention to provide a precharge method of a semiconductor memory device to accomplish the above object.
In one aspect, the present invention is directed to a semiconductor memory device semiconductor memory device comprising a plurality of memory cell array banks, each memory cell bank being partitioned into a plurality of memory cell array blocks, each memory cell array block comprising a predetermined number of partial blocks connected respectively to a predetermined number of groups of a plurality of partial local data input/output line pairs, the local data input/output line pairs being in turn connected respectively to a predetermined number of groups of a plurality of global data input/output line pairs. A plurality of switching means are connected respectively between the predetermined number of groups of the plurality of partial local data input/output line pairs, the switches being activated in response to a precharge signal for connecting the predetermined number of groups of the plurality of partial local data input/output line pairs. A predetermined number of precharge means precharge the predetermined number of groups of the plurality of partial local data input/output line pairs of each memory cell array block in response to the precharge signal.
In another aspect, the present invention is directed to a method of precharging a semiconductor memory device. First, a plurality of memory cell array banks are partitioned into a plurality of memory cell array blocks, each memory cell array block comprising a predetermined number of partial blocks connected respectively to a predetermined number of groups of a plurality of partial local data input/output line pairs, the local data input/output line pairs being in turn connected respectively to a predetermined number of groups of a plurality of global data input/output line pairs. The predetermined number of groups of the plurality of partial local data input/output line pairs are connected by a plurality of switching means, the switches being activated in response to a precharge signal for connecting the predetermined number of groups of the plurality of partial local data input/output line pairs. The predetermined number of groups of the plurality of partial local data input/output line pairs of each memory cell array block are precharged by a predetermined number of precharge means in response to the precharge signal.
In a first preferred embodiment of the apparatus and method, each of the plurality of switching means comprises a first NMOS transistor which is turned on in response to the above precharge signal.
In a second preferred embodiment, each of precharge means comprises second and a third NMOS transistors which are connected serially between said partial local data input/output line pairs, and which are turned on in response to said precharge signal; and a fourth NMOS transistor which is connected between said partial local data input/output line pairs, and which is turned on in response to said precharge signal.
REFERENCES:
patent: 5781495 (1998-07-01), Arimoto
patent: 6104653 (2000-08-01), Proebsting
patent: 6151269 (2000-11-01), Iosaka et al.
patent: 6175532 (2001-01-01), Ooishi
patent: 6181641 (2001-01-01), Lee et al.
Mills & Onello LLP
Nguyen Tan T.
Samsung Electronics Co,. Ltd
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