Precharge system in a SRAM

Details Precharge system in a SRAM Precharge system in a SRAM

1987-12-17

1990-11-20

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

36523003, 3652335, G11C 700

Patent

active

049723731

ABSTRACT:
A precharge system of the divided bit line types for a SRAM (Static Random Access Memory) reduces the active current consumption and bit line peak current by decreasing the number of bit lines to be precharged at any one time during a precharge cycle. For this, the system has a block selection signal generator that responds to certain column addresses with a block selection signal. A sub-block selection signal generator responds to certain addresses among the remaining column addresses with a sub-block selection signal. A precharge decoder responds to pulses from the pulse generator and the block selection signal with a block selection precharge signal. A divided bit line precharge decoder responds to the sub-block selection signal and block selection precharge signal with a pulse for precharging only a certain sub-block of a certain block of the array of memory cells of the SRAM. A column predecoder responds to the block and sub-block selection signals with a block selecting pulse, and a column decoder responds to the block selecting pulse and the remaining column addresses to connect certain bit lines of the sub-block with a data line. The advantages of this are to reduce the power consumption of such a SRAM chip, and the noise in its power supply voltage, by precharging of only a portion of the whole number of bit lines at any one time.

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Okazaki, N. et al., "A 30 ns 256K Full CMOS SRAM", IEEE International Solid-State Circuits Conf., 1986, pp. 204-205.
Ichinga, K. et al., "25 ns 266K.times.1/64K.times.4 CMOS SRAM", IEEE International Solid-State Circuits Conf., 1986, pp. 248-249.
Minato, O. et al., "High Density SRAMS", Digest of Papers, 1987 IEEE International Solid-State Circuits Conference, Feb. 1987, pp. 260 to 261 & 418.
Sasaki, K. et al., "A 15-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1067 to 1071.
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