Precharge of a dram data line to an intermediate voltage

Details Precharge of a dram data line to an intermediate voltage Precharge of a dram data line to an intermediate voltage

1985-10-04

1988-04-26

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, 365207, G11C 1134, G11C 1140

Patent

active

047409215

ABSTRACT:
A dynamic random access memory has data line pair which receives data from a selected pair of bit lines. Coupled to the data line pair is a secondary amplifier for amplifying the data provided to the data line pair from the bit line pair. The secondary amplifier has a maximum gain when the inputs are at a voltage intermediate a power supply voltage. Prior to the pair of bit lines being coupled to the data line pair, the data lines are biased to the intermediate voltage which is in the range of maximum gain of the secondary amplifier so that the secondary amplifier will operate at maximum gain which results in increased speed of operation of the dynamic random access memory.

REFERENCES:
patent: 4367540 (1983-01-01), Shimohigashi
patent: 4467456 (1984-04-01), Oritani
patent: 4528646 (1985-07-01), Ochii et al.
patent: 4542483 (1985-09-01), Procyk
patent: 4570243 (1986-02-01), Sud et al.
patent: 4584672 (1986-01-01), Schutz et al.
patent: 4601017 (1986-07-01), Mochizuki et al.
patent: 4608670 (1986-08-01), Duvvury et al.

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