Precharge control signal generating circuit

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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Details

C365S189090, C365S189110

Reexamination Certificate

active

06233188

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a precharge control signal generating circuit of a semiconductor device, particularly of a semiconductor memory operating at a low voltage.
2. Description of the Related Art
In a semiconductor memory, a large number of memory cells storing data are arranged and connected in a matrix form by a bit line pair (paired two bit lines) in a column direction and a word line in a row direction. This bit line pair is equalized to a predetermined precharge voltage by a precharge control circuit during a precharge period. The precharge control circuit is controlled by a precharge control signal. The details are disclosed in, for example, Japanese Patent Application Laid-open No. Hei. 6-68666.
The foregoing conventional technique has the following problem to be solved.
When a power source voltage of a semiconductor memory is designed to be low, a potential difference between a gate and a source of an NMOS transistor constituting the precharge control circuit becomes small. As a result, there remains a problem to be solved that the NMOS transistor becomes hard to turn on, and a time required to equalize the bit line pair becomes long.
SUMMARY OF THE INVENTION
In order to solve the above problem, according to a first aspect of the invention, a precharge control signal generating circuit in a precharge control circuit of a semiconductor memory comprises a complementary amplifier for receiving a precharge generation signal and outputting a precharge control signal; an operation power source supplying circuit for supplying an operation power source to the complementary amplifier, the circuit having a first electrode connected to a power source voltage of a device and a second electrode connected to a first electrode of the complementary amplifier; a level shifter for receiving a part of the precharge generation signal, raising its level to a value higher than the power source voltage of the device by a predetermined value, and transmitting it to the operation power source supplying circuit; and a capacitor for receiving a part of an output of the level shifter, supplying it to the first electrode of the complementary amplifier, and pumping the operation power source of the complementary amplifier by a predetermined value.
According to a second aspect of the invention, the precharge control signal generating circuit of the first aspect further comprises a pulse expansion circuit for expanding a pulse width of the precharge generation signal inputted to the complementary amplifier, and a timing when the complementary amplifier is tuned off is made coincident with or delayed from a timing when the operation power source supplying circuit for supplying the operation power source is turned off.
According to a third aspect of the invention, the precharge control signal generating circuit of the first aspect receives a part of the output of the level shifter, amplifies it, and adds it to the precharge control signal.
According to a fourth aspect of the invention, the precharge control signal generating circuit of the first aspect further comprises a second level shifter for receiving a part of the output of the level shifter and raising its level; and a second operation power source supplying circuit for supplying the operation power source to the complementary amplifier, the circuit having a first electrode connected to a voltage exceeding the predetermined value, and a second electrode connected to the first electrode of the complementary amplifier, whereby a discharged charge of the capacitor is compensated.


REFERENCES:
patent: 5606524 (1997-02-01), Ozaki et al.
patent: 5933373 (1999-08-01), Takahashi

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