Precharge control circuit of pseudo SRAM

Details Precharge control circuit of pseudo SRAM Precharge control circuit of pseudo SRAM

2006-06-06

2006-06-06

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S229000

Reexamination Certificate

active

07057952

ABSTRACT:
A precharge control circuit of a pseudo SRAM including a precharge set signal generation unit configured to output a precharge set signal, a precharge standby signal generation unit configured to output a precharge standby signal, a precharge signal output unit configured to output a precharge signal in response to the precharge set signal and the precharge standby signal, a first precharge control unit configured to forcedly control the output signal of the precharge standby signal generation unit such that the precharge signal is generated in a period where a chip select signal is disabled, in the case where the chip select signal is disabled long for a first time, and a second precharge control unit configured to forcedly control the output signal of the precharge standby signal generation unit such that the precharge signal is generated in a period where the chip select signal is disabled, in the case where the chip select signal is disabled long for a second time longer than the first time, wherein the precharge signal is generated in response to the operation of the first precharge control unit or the second precharge control unit.

REFERENCES:
patent: 5289424 (1994-02-01), Ito et al.
patent: 5802594 (1998-09-01), Wong et al.
patent: 5998977 (1999-12-01), Hsu et al.
patent: 6061759 (2000-05-01), Guo
patent: 6147898 (2000-11-01), Yamada
patent: RE37176 (2001-05-01), Kajigaya et al.
patent: 6243312 (2001-06-01), Kim
patent: 6813216 (2004-11-01), Lee
patent: 2004/0263206 (2004-12-01), Liu

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