Precharge circuitry in RAM circuit

Details Precharge circuitry in RAM circuit Precharge circuitry in RAM circuit

1999-06-30

2000-08-01

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Precharge

365154, G11C 700

Patent

active

060976519

ABSTRACT:
A random access memory (RAM) device includes a buffer in the memory cell to isolate the latching circuit from the read bit line. Consequently, read disturb errors caused by capacitive loading on the read bit line are avoided. Further, the precharge requirements on the write bit line are simplified because the buffer permits optimization of the latching circuit in the memory cell. The RAM device includes a precharge circuit that precharges the write bit line to a ground reference voltage prior to performing write operations. By precharging the write bit line to ground reference voltage, write disturb problems caused by capacitive loading on the write bit line are avoided. Further, by coupling the write bit line to ground reference voltage, little or no power is consumed by precharging the write bit line.

REFERENCES:
patent: 4845676 (1989-07-01), Lohlein et al.
patent: 5239502 (1993-08-01), Carlstedt
patent: 5353251 (1994-10-01), Uratani et al.
patent: 5687325 (1997-11-01), Chang
patent: 6011711 (2000-01-01), Hodges et al.

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