Preamplification method and apparatus for dram sense amplifiers

Details Preamplification method and apparatus for dram sense amplifiers Preamplification method and apparatus for dram sense amplifiers

1988-06-23

1989-08-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365207, 307530, G11C 1300, G11C 1140

Patent

active

048581933

ABSTRACT:
A preamplifier is provided between a sense amplifier and a memory cell array at each bit line pair lead from a memory cell array. The preamplifier amplifies a potential difference between bit lines at the time of reading information from the memory cell and outputs the same to the sense amplifier. More specifically, the preamplifier charges a step-up capacitor and a step-down capacitor connected in parallel between the bit lines, and then connects these step-up capacitor and step-down capacitor to one input terminal of the sense amplifier in a positive direction and to the other input terminal in a negative direction, respectively. As a result, a potential of the one bit line is boosted and a potential of the other bit line is dropped.

REFERENCES:
patent: 4025907 (1977-05-01), Karp et al.
International Solid-State Circuits conference Digest of Technical Papers, "A Sense-Signal Doubling Circuit for DRAMs" by Kraus Rainer, pp. 16-17.

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