Pre-pattern surface modification for low-k dielectrics using...

Details Pre-pattern surface modification for low-k dielectrics using... Pre-pattern surface modification for low-k dielectrics using...

2001-10-25

2004-04-13

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S692000

Reexamination Certificate

active

06720247

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of forming interconnect layers in a semiconductor device and more specifically to patterning low-k dielectric films.
BACKGROUND OF THE INVENTION
As the density of semiconductor devices increases, the resistance-capacitance (RC) delay time in the back-end-of the-line (BEOL) increases and dominates the circuit performance. To reduce RC delay time at BEOL, the demands on interconnect layers for connecting the semiconductor devices to each other also increase. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects and from traditional silicon-dioxide-based dielectrics to low-k dielectrics, such as organo-silicate glass (OSG). Semiconductor fabrication processes for working with the copper interconnects and newer low-k dielectrics are still needed.
As compared to the traditional subtractive plasma dry etching of aluminum, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed. In a damascene process, the IMD (intra-metal dielectric) is formed first. The IMD is then patterned and etched to form trenches for the interconnect lines. If connection vias have not already been formed, a dual damascene process may be used. In a dual damascene process, an ILD (interlevel dielectric) is deposited before the IMD. An etch-stop layer, such as SiN, can be optionally used in between the IMD and the ILD. The via is formed in the ILD for connection to lower interconnect levels and the trench is formed in the IMD. A barrier layer and a copper seed layer are then deposited over the structure. The barrier layer is typically tantalum nitride or some other binary transition metal nitride. The copper layer is electrochemically deposited (ECD) using the seed layer over the entire structure. The copper is then chemically-mechanically polished (CMP'd) to remove the copper from over the IMD, leaving copper interconnect lines and vias. A metal etch is thereby avoided.
When low-k dielectrics such as OSG are used for the IMD and ILD, a problem known as resist poisoning occurs. Resist poisoning occurs during a patterning step such as via pattern or trench pattern. It is a result of the interaction between a DUV (deep ultra-violet) resist and low-k films. Resist poisoning causes poor resist sidewall profiles, resist scumming, and large CD variations. Furthermore, the required resist exposure dose to achieve the target CD becomes too high and varies with film aging. A process to reduce or eliminate resist poisoning in low-k dielectrics is therefore desired.
SUMMARY OF THE INVENTION
The invention is a surface treatment for low-k films that improves patterning. The low-k film is treated with a dry plasma process to eliminate or significantly reduce resist poisoning. A gas chemistry of H
2
with an inert gas such as Ar or N
2
is used. The H
2
plasma treatment can be performed at various stages in the semiconductor fabrication process with or without the presence of resist. For example, this treatment can be applied to as-deposited low k films before patterning (pre-treatment) or to stripping photo resist for lithograph rework.
An advantage of the invention is providing a treatment to reduce or eliminate resist poisoning of low-k dielectric films.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.


REFERENCES:
patent: 5849640 (1998-12-01), Hsia et al.
patent: 6110648 (2000-08-01), Jang
patent: 6153519 (2000-11-01), Jain et al.
patent: 6362109 (2002-03-01), Kim et al.
patent: 6472335 (2002-10-01), Tsai et al.
patent: 6475707 (2002-11-01), Yu

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