Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-05-15
2004-03-02
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230010, C365S230040, C365S230060, C365S230080
Reexamination Certificate
active
06700822
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention generally relates to a method used in semiconductor memory manufacturing and, more particularly, to a method of word line addressing in semiconductor memory devices in the fabrication of integrated circuits (ICs).
(2) Description of Prior Art
SRAMs are an important volatile memory used in applications where fast access speed is desired. In a typical SRAM memory cell, the logic state of the cell is held at a level using a form of latch. While larger and therefore more costly than a dynamic random access memory (DRAM) cell, the SRAM has a faster access time and does not require periodic refreshing. The SRAM memory cells are arranged in one or more arrays and an address decoder is used to select a desired memory cell within an array.
FIG. 1
contains a block diagram of a typical X-decoder used in a semiconductor memory device
60
to select one or more memory cells to be read or written. A clock signal
10
and control signal
12
are applied to the internal clock generator circuit
14
. The output of the internal clock generator circuit is the global clock (gclk)
16
. A binary address
18
is applied to a buffer
20
, the output of which is applied to a pre-decoder
22
. The binary address
18
is comprised of n bits where 2
n
indicates the total number of word lines
38
. The gclk
16
and the pre-decoded address out of the pre-decoder
22
are applied to a global X-address latch
24
. The global X-address latch
24
holds a new m-bit address Xp
26
on each rising edge (for example) of the gckl
16
. The global address signal Xp
26
is applied to the global X-decoder
28
, selecting one of the 2
m
main word lines (MWL)
30
. The gclk
16
is also applied to the local X-address latch
32
, which then holds a new local address X
0
34
on each rising edge (for example) of the gckl
16
. Each local address X
0
34
is p bits in width allowing selection of one of 2
p
local word lines
38
from the selected main word line
30
. The number of local address lines X
0
34
(p) plus the number of global address lines Xp
26
(m) is equal to the number of input address lines
18
(n). Thus, there are a total of 2
(p+m)
(or 2
n
) local word lines that are addressable. The local word address (X
0
)
34
is applied to the local X-decoder
36
to select one of the 2
p
word lines
38
from the globally selected main word line (MWL)
30
.
FIG. 2
describes the timing relationship between signals in the X-decoder block diagram of FIG.
1
. Referring now to both FIG.
1
and
FIG. 2
, notice that gclk
16
follows clock
10
after a propagation delay. Another delay following application of the gclk
16
, global address signals (Xp)
26
a
and
26
b
are generated on the output of the global X-address latch
24
. Global address signal (Xp)
26
a
illustrates one valid address occurring after the first pulse of the clock
10
and global address signal (Xp)
26
b
illustrates a different valid address occurring after the second pulse of the clock
10
. Signals on main word lines (MWL)
30
a
and
30
b
correspond to decoding of global address signals (Xp)
26
a
and
26
b
, respectively after a propagation delay. Signals on main word lines (MWL)
30
a
and
30
b
are indicative of two distinct main word lines (MWL)
30
a
and
30
b
being selected. Signal X
0
34
follows gclk
16
after a brief delay. Signals on the distinct word lines
38
a
and
38
b
correspond to the aforementioned main word lines (MWL)
30
a
and
30
b
. Word line
38
a
is selected when both X
0
34
and main word line (MWL)
30
a
are high. Word line
38
b
is selected when both X
0
34
and main word line (MWL)
30
b
are high. Unfortunately, at time t
1
main word line (MWL)
30
a
is making a high to low transition while main word line (MWL)
30
b
is making a low to high transition. This occurs while X
0
34
is high and results in a glitch
40
creating a condition where both word lines
38
a
and
38
b
are selected.
During the period where word lines
38
a
and
38
b
are selected, data may be inadvertently written into or read from an improper memory cell location resulting in data corruption or programmed function failure. One method to avoid this problem is to delay the application of signal X
0
34
slightly. However, this will degrade the desired speed performance of the memory.
Referring now to
FIG. 3
, schematically illustrating a typical circuit for the local X-decoder
36
of
FIG. 1. A
first NMOS transistor
42
is provided with its source terminal connected to signal ground and its drain terminal connected to word line
38
. Signal MWLB
31
, which is the complement of signal MWL
30
, is provided from the global X-decoder
28
and is applied to the gate terminal of first NMOS transistor
42
. A PMOS transistor
44
is provided with its source terminal connected to word line
38
. Signals X
0
34
(supplied by the local X-address latch
32
) and MWLB
31
are connected to the drain and gate terminals of PMOS transistor
44
, respectively. XOB
35
which is the complement of X
0
34
(also supplied from the local X-address latch
32
) is applied to the gate terminal of a second NMOS transistor
46
. The drain and source terminals of second NMOS transistor
46
are connected to word line
38
and signal ground, respectively.
Referring now to
FIGS. 3 and 4
, a description of the operation of a prior art local X-decoder is given. Signal clock
10
initiates each addressing sequence and completes said addressing within one cycle of clock
10
. When not addressed, MWLB
31
is high (logic
1
) pulling word line
38
low (logic
0
) through NMOS transistor
42
. On an addressed word line
38
, the signals MWLB
31
, X
0
34
and XOB
35
become low (logic
0
), high (logic
1
) and low, respectively, some delay after a rising edge (for example) of clock
10
. This method requires that the signal MWLB
31
be held low during the cycle duration rather than being prepared to address the next memory location thereby limiting the cycle time of clock
10
.
Other approaches related to improving memory device decoding and addressing exist. U.S. Pat. No. 5,311,474 considered to Harada describes a method where a pre-decoding circuit used in a semiconductor memory generates complementary decoding signals with approximately equal time delays. This results in reduced current and an improvement in decoding speed. U.S. Pat. No. 5,351,217 considered to Jeon teaches a method reducing the word line capacitance in a semiconductor memory while enabling and disabling the word line. This is accomplished using a modified row decoder, reset level converter and word line driver/controller and results in speed improvement in the memory device. U.S. Pat. No. 5,428,577 considered to Yumitori et al. teaches a method using a word line voltage boosting circuit in a pre-decoder. The boosting circuit charges the signal path prior to application of the word line drive signal thereby improving performance. U.S. Pat. No. 5,852,585 considered to Koshizuka teaches a method where faster addressing speed is achieved by pre-decoding an address prior to application of the address to a latch. The pre-decoding is done simultaneously with the generation of an internal latching pulse thereby improving the access time. U.S. Pat. No. 6,055,206 considered to Tanizaki et aL teaches a method where a hierarchical supply is provided to reduce standby current in a large semiconductor memory. U.S. Pat. No. 6,072,732 considered to McClure describes a method whereby a reset is applied after a fixed delay following activation of a word line in a memory device during a memory write sequence. This minimizes access time and prevents simultaneous writing of sequentially addressed word lines.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a method that prevents simultaneous addressing in the word line in a semiconductor memory, thereby eliminating memory errors.
Another object of the present invention is to provide a method that prevents simultaneous addressing in t
Ackerman Stephen B.
Elms Richard
Luu Pho M.
Pike Rosemary L. S.
Saile George O.
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