Static information storage and retrieval – Read/write circuit – Precharge
Patent
1991-09-25
1993-11-02
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Precharge
365204, 365208, G11C 706
Patent
active
052589552
ABSTRACT:
A pre-charging and reading circuit for an integrated circuit memory comprises a pre-charging transistor and an inverter looped between the source and the gate of the pre-charging transistor to constitute a servo-control circuit imposing a set value of pre-charging voltage on the bit line. To accelerate the pre-charging without causing deterioration in the operation during the reading proper, the characteristics of the servo-control circuit are modified during a pre-charging stage so that the set value voltage imposed during the pre-charging stage is higher than the set value voltage imposed during the reading stage. A sequencer puts a transistor N'1 or a transistor N1 into operation as an N channel transistor of the inverter, depending on whether the stage in progress is a pre-charging stage or a reading stage.
REFERENCES:
patent: 3932848 (1976-01-01), Porat
patent: 4851894 (1989-07-01), de Ferron
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 4947375 (1990-08-01), Gaultier
patent: 4962482 (1990-10-01), Jinbo
patent: 5007026 (1991-04-01), Gaultier
patent: 5012448 (1991-04-01), Matsuoka et al.
Patent Abstracts of Japan, vol. 6, No. 75 (P-114), published Jan. 22, 1982.
LaRoche Eugene R.
Le Vu
SGS-Thomson Microelectronics S.A.
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