Pre-charged slave latch with parallel previous state memory

Details Pre-charged slave latch with parallel previous state memory Pre-charged slave latch with parallel previous state memory

1994-11-30

1996-02-13

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523008, 365203, 36523001, G11C 700

Patent

active

054916631

ABSTRACT:
According to the present invention, a method and structure for using precharged data path techniques in those applications where it is necessary to retain the previous state of data is presented. In the preferred embodiment, a Pre-Charged Slave Latch with Parallel Previous State Memory circuit of a burst SRAM employs a parallel memory element configuration. In conjunction with this parallel memory element configuration, three stages are disclosed to implement a pre-charged data path technique for a burst SRAM memory. First, external data is loaded into the Pre-Charged Slave Latch with Parallel Previous State Memory circuit. Next, during a burst address sequence state of the Burst SRAM, the previous address state is allowed to propagate through the address decode path of the burst SRAM. Finally, the output signal of the Pre-Charged Slave Latch with Parallel Previous State Memory is precharged to an inactive state in parallel with other circuit elements of the pre-charged address decode path. Thus, the advantages of pre-charged data path techniques such as increased gate fanout in the address decode path and increased memory access which results in faster speed may be enjoyed in conjunction with burst SRAM memories and other applications where it is necessary to retain a previous state of data.

REFERENCES:
patent: 5113374 (1992-05-01), Matsui
patent: 5319759 (1994-06-01), Chan
patent: 5392239 (1995-02-01), Margulis et al.

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