Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-02
2004-09-07
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185020, C365S185210, C365S203000
Reexamination Certificate
active
06788583
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to flash memory cell devices and more specifically, to improvements in pre-charge reading methods for reading a charge previously stored in a dual bit dielectric memory cell structure.
BACKGROUND OF THE INVENTION
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO
2
), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate are a channel region positioned below the vertical stack and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Si-SiO
2
energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the Si-SiO
2
interface under the influence of the control gate electrical field and gain sufficient energy to cross the barrier.
Once programmed, the negative charge on the floating gate disburses across the semi conductive gate and has the effect of increasing the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate. During a “read” of the memory cell, the programmed state (e.g. negative charge stored on the gate), or the non-programmed state (e.g. neutral charge stored on the gate) of the memory cell can be detected by detecting the magnitude of the current flowing between the source and drain at a predetermined control gate voltage.
More recently dielectric memory cell structures have been developed. A conventional array of dielectric memory cells
10
a
-
10
f
is shown in cross section in FIG.
1
. Each dielectric memory cell is characterized by a vertical stack of an insulating tunnel layer
18
, a charge trapping dielectric layer
22
, an insulating top oxide layer
24
, and a polysilicon control gate
20
positioned on top of a crystalline silicon substrate
15
. Each polysilicon control gate
20
may be a portion of a polysilicon word line extending over all cells
10
a
-
10
f
such that all of the control gates
20
a
-
20
g
are electrically coupled.
Within the substrate
15
is a channel region
12
associated with each memory cell
10
that is positioned below the vertical stack. One of a plurality of bit line diffusions
26
a
-
26
g
separate each channel region
12
from an adjacent channel region
12
. The bit line diffusions
26
form the source region and drain region of each cell
10
. This particular structure of a silicon channel region
22
, tunnel oxide
12
, nitride
14
, top oxide
16
, and polysilicon control gate
18
is often referred to as a SONOS device.
Similar to the floating gate device, the SONOS memory cell
10
is programmed by inducing hot electron injection from the channel region
12
to the charge trapping dielectric layer
22
, such as silicon nitride, to create a non volatile negative charge within charge traps existing in the nitride layer
22
. Again, hot electron injection can be achieved by applying a drain-to-source bias along with a high positive voltage on the control gate
20
. The high voltage on the control gate
20
inverts the channel region
12
while the drain-to-source bias accelerates electrons towards the drain region. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Si-SiO
2
energy barrier between the channel region
12
and the tunnel oxide
18
. While the electrons are accelerated towards the drain region, those electrons which collide with the crystalline lattice are re-directed towards the Si-SiO
2
interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier. Because the nitride layer stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a drain charge storage region that is close to the drain region. For example, a charge can be stored in a drain bit charge storage region
16
b
of memory cell
10
b
. The bit line
26
b
operates as the source region and bit line
26
c
operates as the drain region. A high voltage may be applied to the channel region
20
b
and the drain region
26
c
while the source region
26
b
is grounded.
Similarly, a source-to-drain bias may be applied along with a high positive voltage on the control gate to inject hot electrons into a source charge storage region that is close to the source region. For example, grounding the drain region
26
c
in the presence of a high voltage on the gate
20
b
and the source region
26
b
may be used to inject electrons into the source bit charge storage region
14
b.
As such, the SONOS device can be used to store two bits of data, one in each of the source charge storage region
14
(referred to as the source bit) and the charge storage region
16
(referred to as the drain bit).
Due to the fact that the charge stored in the storage region
14
only increases the threshold voltage in the portion of the channel region
12
beneath the storage region
14
and the charge stored in the storage region
16
only increases the threshold voltage in the portion of the channel region
16
beneath the storage region
16
, each of the source bit and the drain bit can be read independently by detecting channel inversion in the region of the channel region
12
between each of the storage region
14
and the storage region
16
. To “read” the drain bit, the drain region is grounded while a voltage is applied to the source region and a slightly higher voltage is applied to the gate
20
. As such, the portion of the channel region
12
near the source/channel junction will not invert (because the gate
20
voltage with respect to the source region voltage is insufficient to invert the channel) and current flow at the drain/channel junction can be used to detect the change in threshold voltage caused by the programmed state of the drain bit.
Similarly, to “read” the source bit, the source region is grounded while a voltage is applied to the drain region and a slightly higher voltage is applied to the gate
20
. As such, the portion of the channel region
12
near the drain/channel junction will not invert and current flow at the source/channel junction can be used to detect the change in threshold voltage caused by the programmed state of the source bit.
In a typical flash memory array, the structure wherein each of multiple cells shares a common word line with adjacent cells creates a problem in reading each cell. For example, when reading bit
14
b
, the bit line
26
b
is grounded while a voltage is applied to bit line
26
c
and to the gate
20
b
. Current flow at the bit line
26
c
(representing electrons pulled from the grounded bit line
26
b
through the channel region
12
b
) is used to detect threshold voltage of the cell
10
b
to determine the programmed state of the source bit
14
b.
A problem is that because the gate
20
b
is coupled by the same wordline as gates
20
c
-
20
f
, the gate
20
c
is also biased high. As such, a transient current may also flow into the bit line
26
c
through the cell
20
c
thereby causing a false read of the bit
14
b
. To prevent such a current flow, a pre-charge bias is typically applied to the bit
Chen Pau-ling
Hamilton Darlene G.
He Yi
Le Binh
Liu Zhizheng
Advanced Micro Devices , Inc.
Renner Otto Boisselle & Sklar
Yoha Connie C.
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