Power transistor arrangement and method for fabricating it

Details Power transistor arrangement and method for fabricating it Power transistor arrangement and method for fabricating it

2007-07-31

2007-07-31

Baumeister, B. William (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S330000, C257S341000, C257SE21418

Reexamination Certificate

active

10987189

ABSTRACT:
In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).

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Widmann et al., “Technologie Hochintegrierter Schaltungen”, Springer, 1996, (4 pages).

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