Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-24
2002-02-05
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S335000, C257S341000
Reexamination Certificate
active
06344676
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 99-10799, filed on Mar. 29, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device, and more particularly, to a high power MOS transistor of having a low on-resistance and a high breakdown voltage.
High power MOS transistors require a high breakdown voltage, a low on-resistance and a high switching speed. The on-resistance is made up of a channel resistance, a JFET resistance, an accumulation resistance, and a drift resistance. Of these, the drift resistance is directly related to the breakdown voltage.
FIG. 1
is a plan view of a group of high power MOS transistors, each having a conventional polygonal unit cell
100
. Referring to
FIG. 1
, the hexagonal unit cells
100
are arranged such that they each have the same separation distance d, and such that the high power MOS transistors each have a high breakdown voltage and a low on-resistance.
FIG. 2
is a sectional view of the MOS transistors taken along the line II-II′ of FIG.
1
. Referring to
FIG. 2
, the MOS transistors include a drain region
200
, a drain electrode
210
, a drift layer
220
, a plurality of body regions
230
, a deep p
+
region
232
, a plurality of source regions
240
, a gate insulating layer
250
, a gate electrode
252
, and a source electrode
260
.
The drain region
200
and the drift layer
220
are both of a first conductivity type and the drift layer is formed on one side of the drain region
200
. A plurality of body regions
230
, of a second conductivity type, are formed in the upper regions of the drift layer
220
. A pair of source regions
240
, of the first conductivity type, are formed in each of the body regions
230
. A deep p
+
region
232
is then formed between each pair of source regions
240
. A gate insulating layer
250
is formed on the surface of the body region
230
between adjacent body regions
230
, at a point where a channel is to be formed during the operation of a device. A gate electrode
252
is formed on the gate insulating layer
250
; a source electrode
260
is formed to be electrically connected to the source region
240
; and a drain electrode
210
is formed to be electrically connected to the drain region
200
.
As shown in
FIG. 1
, each cell has an inner segment
132
and a middle segment
160
, and an outer segment
170
. The outer segment
170
corresponds to the spacing between the gate electrode
252
and the source electrode
260
, and has a width ‘o.’ The middle segment
160
corresponds to the overlap between the source electrode
260
and the source region
240
, and has a width of ‘m.’ The inner segment
132
corresponds to the portion of the p
+
body
232
that is not covered by the source region
240
.
In a conventional high power MOS transistor, unit cells are formed in a polygonal shape to increase the channel density per unit area, so as to reduce the on-resistance of the device. However, when a high voltage is applied between a source electrode
260
and a drain electrode
210
in an off-state, a spherically-shaped depletion region is formed, which lowers the breakdown voltage. However, if the resistivity and the thickness of the materials of the device are increased in an effort to increase the breakdown voltage of the device, the on-resistance of the device will be likewise increased.
With respect to the capacitive components of a conventional high power MOS transistor, the switching speed is determined by C
gd
, i.e., the capacitance between the gate electrode
252
and the drain electrode
210
. The value of C
gd
is determined by the area of the drift layer
220
between adjacent body regions
230
that is covered by the gate electrode
252
. If this area is increased, C
gd
is also increased, reducing the switching speed of the device.
When a high power MOS transistor is formed of polygonal unit cells, the total area over which the gate electrode
252
covers the drift layer
220
between adjacent body regions
230
is increased. As a result, the high power MOS transistor has a high C
gd
value, and the switching speed of the device is reduced.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a high power MOS transistor having a high breakdown voltage, a low on-resistance, and a high switching speed.
It is another objective of the present invention to provide an insulated gate bipolar transistor having a high breakdown voltage, a low on-resistance, and a high switching speed.
Accordingly, to achieve the above objectives, a power semiconductor device according to the present invention includes a drain region of a first conductivity type, a drift layer of the first conductivity type formed over a first surface of the drain region, a body region of a second conductivity type formed in the drift layer, the body region comprising a body frame region, and a plurality of parallel body strips, both ends of each of the plurality of body strips being connected to the frame region, a source region of the first conductivity type formed in the body region, having a depth more shallow than that of the body region, a source electrode formed over the source region, a drain electrode formed over a second surface of the drain region opposite to the first surface, a gate insulating layer formed over a channel region in the drift layer, and a gate electrode formed over the gate insulating layer.
The power semiconductor device may further comprise a highly-doped drift layer formed in the drift layer under the gate electrode. In this case, the highly-doped drift layer is doped more highly than the drift layer.
The distance between adjacent body strips is preferably sufficiently narrow to form a planar junction between the body strips, and the radius of curvature of a corner of the body region is preferably greater than or equal to 200 &mgr;m.
The first conductivity type is preferably n-type, but it may also be p-type. The power semiconductor device is preferably a high power MOS transistor.
To achieve the above objectives, a power semiconductor device according to the present invention may also include a collector region of a first conductivity type, a drift layer of a second conductivity type formed over the collector region, a base region of the first conductivity type formed in the drift layer, the base region comprising a base frame region, and a plurality of parallel base strips, both ends of each base strip being connected to a frame region, an emitter region of the second conductivity type formed in the base region, having an emitter depth more shallow than a base depth of the base region, a gate insulating layer formed over a channel region in the drift layer, and a gate electrode formed over the gate insulating layer.
The power semiconductor device may further comprise a highly-doped drift layer formed in the drift layer under the gate electrode. In this case, the highly-doped drift layer is doped more highly than the drift layer.
The distance between adjacent base strips is preferably sufficiently narrow to form a planar junction at corners of the base strips, and the radius of curvature of a corner of the base region is preferably greater than or equal to 200 &mgr;m.
The first conductivity type is preferably p-type, but may also be n-type. The power semiconductor device is preferably an insulated gate bipolar transistor.
The power semiconductor device according to the present invention has a low on-resistance, a high breakdown voltage and a high switching speed.
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patent: 4072975 (1978-02-01), Ishitani
patent: 4145700 (1979-03-01), Jambotkar
patent: 4376286 (1983-03-01), Lidow et al.
patent: 4642666 (1987-02-01), Lidow et al.
patent: 4959699 (1990-09-01), Lidow et al.
patent: 5798554 (1998-08-01), Grimaldi et al.
patent: 10-290011 (1998-10-01), None
Choi Young-chull
Jang Ho-cheol
Kim Tae-hoon
Yun Chong-man
Nadav Ori
Samsung Electronics Co,. Ltd.
Thomas Tom
Volentine & Francos, PLLC
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