Power savings with a level-shifting boundary isolation...

Details Power savings with a level-shifting boundary isolation... Power savings with a level-shifting boundary isolation...

2008-04-17

2009-11-24

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S021000, C326S046000

Reexamination Certificate

active

07622955

ABSTRACT:
An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.

REFERENCES:
patent: 2005/0162188 (2005-07-01), Newman
patent: 2008/0007312 (2008-01-01), Clark et al.

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