Power saving by disabling cyclic bitline precharge

Details Power saving by disabling cyclic bitline precharge Power saving by disabling cyclic bitline precharge

2007-11-13

2007-11-13

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S207000, C365S189040

Reexamination Certificate

active

10711982

ABSTRACT:
A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is realized by determining whether a next access operation following a current access operation is a read or write access, and performing a precharge of the bitlines of the array only when a read operation follows the current access operation. A conventional precharge control signal is combined with an external control signal indicating if the next cycle is a read cycle. The combination of the two signals can be used, for example, as input to a simple AND gate to generate an effective precharge signal. The effective precharge signal permits precharging of bitlines only when those bitlines are used for read access in a respective next cycle.

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