Power-on state machine implementation with a counter to...

Details Power-on state machine implementation with a counter to... Power-on state machine implementation with a counter to...

2005-03-22

2005-03-22

Baderman, Scott (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S006130, C714S733000

Reexamination Certificate

active

06871297

ABSTRACT:
An apparatus comprising a controller circuit and a BISR assembly circuit. The controller circuit may be configured to present one or more control signals. The control signals may be configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation. The BISR assembly circuit generally comprises one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution during the BIST and BISR operations. The memory blocks may be remapped in response to the count values during one or more of the BISR operations.

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