Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-21
2004-02-17
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S271000
Reexamination Certificate
active
06693011
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a power MOS element and to a method for producing the same and in particular to a vertical power MOS element whose gate comprises a plurality of trenches and whose source contact and gate contact are located on the front side thereof, while the drain contact is located on the rear side thereof, in such a way that the flow of current through the element is basically perpendicular to the front side and the rear side, i.e. vertical.
BACKGROUND OF THE INVENTION AND PRIOR ART
Vertical power MOSFET structures have been known for quite a time. As early as in 1985 Daisuke Ueda et al. presented a power MOS element provided with a trench gate in “New Vertical Power MOSFET Structure with Extremely Reduced On-Resistance”, IEEE Transactions on Electron Devices, Vol. ED-32, No. 1, January 1985. In this structure the gate is not located laterally on the surface of the wafer but vertically on the side faces of trenches plasma etched anisotropically. The element comprises a full area rear side drain contact and an upper side source contact.
In vertical power MOS transistors of this type the proportion of the channel resistance of the overall turn-on-resistance increases with a decreasing electrical strength. To decrease the power dissipation at the transistor, the chip area has to be enlarged or the channel width of the transistor has to be increased. The trench technology provides for a significantly increased channel width per active transistor area compared to the conventional DMOS technology, since in this case only technology parameters are limiting factors, and not electric parameters as in the case of the DMOS concept.
In “A High-Performance Self-Aligned UMOSFET with a Vertical Trench Contact Structure” by S. Matsumoto et al., IEEE Trans. Electr. Dev., Vol. 41, No. 5, May 1994, a power MOS element is disclosed which, as the sequence of layers, comprises a strongly n-doped source layer, a p-doped channel layer, a weakly n-doped drift layer and a strongly n-doped substrate layer to which the rear side drain contact is attached. Trenches filled with polysilicon, which are insulated towards the top by silicon dioxide, form the gate trenches. The source contact on the upper side of the element is connected to both the source region and to the channel region via a contact hole filled with a metal, to hold both the source region and the channel region at a same potential. By simultaneously contacting the source region and the channel region using a contact hole a space-saving circuit design can be obtained. Since in the formation of the contact hole high aspect ratios form, a metalization which can be deposited conformly must be inserted to fill the contact holes without any empty spaces. Tungsten is used for this.
In “A High-Density Self-Aligned 4-Mask-Planar VDMOS Process” by D. Kinzer et al., Proc.-ISPSD 96, 20 to 23 of May 1996, Maui, USA, pages 243-247, a common method for producing power MOS transistors is illustrated. For the production four masks are usually used, the first mask serving to produce an opening in a field oxide, in which the active cells are to be accomodated. The second mask is the gate mask. The third mask serves as a contact mask, the fourth, and last, mask being the metal mask. This mask separates the source metal from the gate metal. The gate contact is made directly above the active gate over the whole gate width. If this technology is applied to power elements with trench gates, a further masking is additionally necessary to produce the gate trenches. Thus, conventionally five masks are used to produce vertical power elements with gate trenches.
While Ueda, Matsumoto and Kinzer describe vertical power MOS elements which are formed on or in a semiconductor substrate doped in a layered way, Richard K. Williams et al. describe a vertical power element with locally formed p- and n-regions for forming the channel region and the source region in “A 30-V P-channel Trench Gated DMOSFET with 900 &mgr;&OHgr;-cm
2
Specific On-Resistance at 2.7 V”, Proc-ISPD 96, 20 to 23 May 1996, Maui, USA, pages 53 to 57.
A full area unmasked production of the doping regions is described in WO 93/26047. A silicon carbide power MOSFET disclosed in there includes an active region and a connecting region. The connecting region serves to increase the electrical strength of the power element towards the cutting edges of it or towards the margin of the wafer in such a way that margin breakdowns at margin surfaces do not limit the power sustaining capability. The active region includes a gate trench insulating towards the drift region, the general region and the source region, which is produced by means of a well-known ion trench etching method. After an oxidation the trench is filled with polysilicon or a metal. The gate trench is contacted via a (polysilicon) gate contact, while a source contact and a drain contact are attached to the front and rear side of the element respectively. Non-contacted trenches in the margin region are provided to form potentially “floating” field plates and field rings respectively.
WO 95/09439 describes a further silicon carbide field effect element. This element includes several gate trenches which are formed in a substrate doped in a layered way. The trenches contain polysilicon as the conductive material which is insulated by means of an insulator. The substrate contains a large area source contact on the upper side and a large area drain contact on the rear side. The gate trenches are contacted by through holes in the source contact and in the insulator which surrounds the conductive material in the gate trench. Several single FET elements are connected in parallel by contacting the conductive gate electrodes by means of a metalization insulated from the source contact, which is arranged above the source contact.
The disadvantage of these well-known power MOS elements is that, after producing the source contact, in a further masking process through holes have to be formed in the source metal contact and the underlying gate insulator to be able to contact the gate electrodes in the gate trenches. If these gate trenches are to be connected in parallel to be able to process high currents, further steps for insulating the through holes towards the gate trenches and for structuring the gate electrode which are arranged above the source electrode are necessary, whereby the method for producing becomes expensive since two metalization layers being above each another are present, which have to be insulated from each other. Furthermore, the well-known power MOS element needs further steps for contacting the channel region which is usually, as is described in Ueda, set to the same potential as the source region.
The U.S. Pat. No. 5,763,915 discloses a DMOS transistor comprising a quadratically branched gate trench in which polysilicon is located which is isolated from the circumferential semiconductor material by a gate oxide. The gate trench defines squares which establish individual transistor cells, one source contact being arranged in each square, the plurality of source contacts, together with the rear side drain contact, forming a plurality of parallel-connected individual transistors which form the DMOS transistor as a whole. The quadratically branched gate trench is connected to a connection trench via a plurality of parallel gate rotors which are also formed as a trench. The source contact is realised by a continuous metal-face above the individual transistors, the source contact being in contact with the source region via through holes by an oxide. The gate contact is connected to the connection trench which is wider than the gate trench and the gate rotors via through holes.
EP-A-0 583 023 discloses a method for producing a DMOS transistor in which six masking steps are used. The DMOS transistor includes a terminating structure with several field rings, every set of adjacent field rings being isolated by an insulation trench so that the field rings can be arranged closely to one another. The field rings a
Vogt Holger
Wahl Uwe
Brock II Paul E
Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung
Glenn Michael A.
Glenn Patent Group
Lee Eddie
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