Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-18
2004-01-13
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S280000
Reexamination Certificate
active
06677202
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to a power MOS device having increased channel width and to a process for forming same.
BACKGROUND OF THE INVENTION
The recent proliferation of portable, battery-powered electronic communication devices has increased the need for low voltage, low on-resistance power MOSFETs for efficient power management. For low voltage MOSFETs, the channel resistance is a large component of the overall on-resistance. Therefore lowering the channel resistance results in a corresponding reduction in on-resistance.
FIG. 1
schematically depicts a prior art device
100
having a planar DMOS stripe configuration on a substrate
101
having a doped upper layer
102
. Upper layer
102
includes doped P-well regions
103
and heavily doped N+ source regions
104
. On an upper surface
105
of upper layer
102
is a gate region
106
that includes an insulating layer
107
and a conductive layer
108
.
One means for reducing channel resistance in a prior art device such as
100
is to increase its channel density in the region
109
of layer
102
underlying gate region
106
. Increasing channel density, however, would require a reduction in device geometry and/or a process modification that may be subject to equipment and technique limitations. The present invention offers a desirable alternative to the increased channel density approach for achieving reduced on-resistance in a power device.
SUMMARY OF THE INVENTION
The present invention is directed to a power MOS device that has increased channel width and comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate.
Further in accordance with the present invention is a process for forming a power MOS device having increased channel width on a semiconductor substrate having a doped upper layer of a first conduction type. A stripe mask is formed on an upper surface of the upper layer, and the upper surface is selectively etched to form a corrugated surface comprising a plurality of parallel corrugations. Following removal of the stripe mask, an insulating layer is formed on the corrugated surface, and an overlying conductive layer is formed on the insulating layer, the insulating and conductive layers comprising a corrugated gate region disposed transversely to the parallel corrugations of the upper surface. A dopant of a second, opposite conduction type is implanted to form a doped well region in the upper layer, and a dopant of the first conduction type is implanted into a portion of the corrugated surface adjacent to the gate, thereby forming a heavily doped source region in the upper layer.
In an alternative procedure for forming a gate, a gate trench having a floor comprising parallel corrugations that substantially correspond to the corrugations in the upper surface is etched into the upper layer. Following lining of the trench floor and sidewalls with an insulating layer, the trench is substantially filled with a conductive material to form a gate trench. A dopant of the first conduction type is implanted into a portion of the corrugated surface adjacent to the gate region, thereby forming a heavily doped source region in the upper layer.
The present invention provides a means of increasing channel width in a power MOS device without requiring reduced device geometry. The increased width of the channel is a consequence of the corrugated surface of its overlying gate region.
REFERENCES:
patent: 4234887 (1980-11-01), Vanderslice, Jr.
patent: 4393391 (1983-07-01), Blanchard
patent: 4748103 (1988-05-01), Hollinger
patent: 4985740 (1991-01-01), Shenai et al.
patent: 4998151 (1991-03-01), Korman et al.
patent: 5019522 (1991-05-01), Meyer et al.
patent: 5119153 (1992-06-01), Korman et al.
patent: 5430315 (1995-07-01), Rumennik
patent: 5541430 (1996-07-01), Terashima
patent: 5804863 (1998-09-01), Rhee
patent: 5897343 (1999-04-01), Mathew et al.
patent: 5977564 (1999-11-01), Kobayashi et al.
patent: 6316813 (2001-11-01), Ohmi et al.
patent: 04144287 (1992-05-01), None
Carlile, Robert N. “Trench Etches in Silicon With Controllable Sidewall Angles”,J. Electrochem, Soc. pp. 2058-2064, (Aug. 1988).
Bean, Kenneth E., “Anisotropic Etching of Silicon”,IEEE Transactions on Electron Devices, pp. 1185-1193, (1978).
Semple Dexter Elson
Zeng Jun
Brock, II Paul E.
Fairchild Semiconductor Corporation
FitzGerald Esq. Thomas R.
Lee Eddie
LandOfFree
Power MOS device with increased channel width and process... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power MOS device with increased channel width and process..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power MOS device with increased channel width and process... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3189005