Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-08
2003-01-07
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S289000
Reexamination Certificate
active
06503786
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to improving the safe operating area (SOA) and the conduction loss of a power semiconductor device operating under “linear” operating conditions. The invention is couched in the terminology of a power metal-oxide-semiconductor field-effect transistor (MOSFET). The same principle applies to devices such as the IGBT (insulated gate bipolar transistor) having similar forward transfer characteristics.
BACKGROUND OF THE INVENTION
For simplicity, the following discussion employs symbols and structures appropriate for a vertical N-Channel double-diffused metal-oxide-semiconductor field-effect transistor (VDMOS). Parallel discussions and conclusions can be drawn for an IGBT by changing the starting material from an N+ type substrate to a P+ type substrate and by substituting the Emitter for the Drain and the Collector for the Source terminals. Similarly, appropriate changes in the polarity of the doping layers will be straightforward to those skilled in the art to apply the discussions to a P-Channel device. Examples of these devices and their manufacture are described in U.S. Pat. Nos. 4,895,810 and 5,262,336. Collectively, these devices can be referred to generically as power MOSFET-type devices.
Commercial VDMOS devices are fabricated using high temperature oxidation, deposition and difflusion processes to create distinctive N− drain, P-body and N+ source regions. The N− drain region and the N+ source region are spaced apart by the P-body region and form with it two back-to-back PN diodes which normally would inhibit current flow from drain to source. If a gate oxide is grown over the P-body region and an electrode is placed insulatively thereupon so as not to electrically short the underlying diffusions and to overlap the body, drain and source diffusions, an N-type conducting channel can be created by field effect through appropriate bias applied to the gate electrode to change the surface of the P-body region into n-type, thereby allowing current to flow in the presence of a drain-source bias. When this gate bias is removed, the surface channel reverts back to P-type and current flow is stopped. A simplified mathematical expression which describes the interaction between the gate voltage and the current flowing from drain to source is given below:
I=&egr;&mgr;W
(
V
GS
−V
TH
)
2
/(2
L t
OX
) (1)
The transconductance, defined as the rate of change of forward current with gate bias is then,
Gm=dI/dV
GS
=&egr;&mgr;W
(
V
GS
−V
TH
)/(
Lt
OX
) (2)
where the symbols carry their traditional meanings: &egr;, permitivity; &mgr;, carrier mobility; W, channel width; L, channel length; t
OX
, gate oxide thickness; V
GS
, gate-source applied voltage; V
TH
, threshold voltage for surface inversion; T, temperature; and G
m
, the transconductance. W, L and t
OX
are affixed by design and process and are invariant with operating temperature, while carrier mobility &mgr; and threshold voltage V
TH
are monotonically-decreasing functions of temperature. A representative threshold voltage vs. temperature curve calculated for a 1000 Å gate oxide is shown in FIG.
1
. This temperature dependence of the threshold voltage is a key cause for instability when operating a given MOSFET at certain currents.
Empirically, mobility has been shown to follow temperature to the (−1.7) power. The combined dependence on temperature by threshold and mobility leads to forward transfer characteristic graphs showing the dependence of device drain-source current ID on the gate-source bias voltage V
GS
. One such typical curve is shown in
FIG. 2
for a commercial VDMOS, APT5020BVR in this case. This graph shows a device user how much current can be expected to flow through the MOSFET at a given gate voltage. The current is plotted at three different temperatures vs. gate voltage. Note that the transconductance, which is the slope of this curve, decreases with temperature. The curves formed at different temperatures are shown here to crisscross through a single point. This point is sometimes referred to as the “zero temperature coefficient point” (ZTCP). The current increases with temperature below this point and decreases with temperature above this point. Device operation above this ZTCP point is thermally stable while below this point operation is not thermally stable.
Instability to operation below the ZTCP point can be understood in the following simplified explanation: When operated below the ZTCP point, if a local region due to any processing or packaging inhomogeneity gets hot, the threshold voltage will drop as shown in FIG.
1
. As the threshold voltage drops, a stronger gate drive or larger difference in the (V
GS
,−V
th
) term in Eq. 1 develops, causing the current to rise. This rising current generates more heat in the local region, which further drives down the threshold voltage. Thus, a positive feedback loop develops, which if unchecked, can cause hot spotting and eventual device failure.
Traditionally, commercial VDMOS are designed with high packing density to minimize resistance per unit area. As such, the current that could be made to flow and the power thus generated far exceeds the heat-dissipative capability of the silicon. Application of the VDMOS transistor as Class A, Class B or Class AB linear amplifiers has shown a propensity for thermal instability and raised concerns for suitability of VDMOS as linear amplifiers.
A prior art solution enabling the VDMOS devices to operate as linear amplifiers is to reduce the packing density of the silicon while maintaining the device size for heat dissipative capability. A common practice, such as described in U.S. Pat. No. 5,095,343, is to eliminate part of the channel from conducting current through eliminating some of the N+ source diffusions shown in
FIGS. 3 and 4
in the said patent.
FIG. 7
shows a conventional VDMOS device with a symmetrical channel.
FIG. 8
shows such a device in which the N+ diffusion is eliminated on one side of the device. By so doing, the transconductance is reduced and, with it, the current level of the ZTCP point. Using this reduced channel device in the same application would effectively mean operation closer to the ZTCP point where current variance due to temperature fluctuation is substantially reduced. A device so created, though superior in linear operation, pays a penalty of higher conduction loss due to increase in on-state resistance for the same operating current.
Accordingly, a need remains for a way to achieve linear operation of a VDMOS transistor and other power MOSFET devices while retaining the advantage of low conduction loss.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to achieve linear operation in power MOSFET type devices while keeping conduction loss low.
One aspect of the invention is a power device in which a portion of the channel has a threshold voltage characteristic that is different from the threshold voltage characteristic of the remainder of the channel. Such a power MOSFET type device achieves linear operation while keeping conduction loss low. An advantage of such a device is that it provides a forward biased safe operating area (FBSOA) higher than a conventional switch mode device of the same design with symmetric threshold characteristics.
A power MOSFET type device according to the invention comprises a substrate of a first dopant type and first and second gate structures disposed on a surface of the substrate and spaced apart thereon. A body region of a second dopant type is formed in the substrate and has first and second spaced-apart channel regions respectively disposed subjacent the first and second gate structures. First and second source regions of the first dopant type are formed in the body region, The first and second channel regions are formed so as to have different gate threshold voltage characteristics.
Preferably, the first channel region has a gate threshold voltage characteristic suffi
Advanced Power Technology Inc.
Chaudhuri Olik
Marger & Johnson & McCollom, P.C.
Pham Hoai
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