Power field effect transistor and manufacturing method thereof

Details Power field effect transistor and manufacturing method thereof Power field effect transistor and manufacturing method thereof

2011-02-22

2011-02-22

Ghyka, Alexander G (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S306000, C438S514000, C438S522000, C438S527000, C257SE21066

Reexamination Certificate

active

07892923

ABSTRACT:
A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate having a wide band gap superficial semiconductor layer, including the steps of forming a screening structure on the superficial semiconductor layer that leaves a plurality of areas of the superficial semiconductor layer exposed, carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer for forming at least one deep implanted region, carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer for forming at least one implanted body region of the MOS transistor aligned with the deep implanted region, carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer for forming at least an implanted source region of the MOS transistor inside the at least one implanted body region, and a low budget activation thermal process of the first and second dopant types suitable to complete the formation of the body region, of the source region, and of the deep implanted region with diffusing the dopants in the substrate.

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V. R. Vathulya et al., “Characterization of Inversion and Accumulation Layer Electron Transport in 4H and 6H-SiC MOSFETs on Impaired P-Type Regions,” IEEE Transactions on Electron Devices, Nov. 2000, pp. 2018-2023, vol. 47, No. 11, IEEE, Piscataway, NJ, US.

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